I am trying to use BeagleBoard RevC in bare metal.
A very simple test reveals that the MPU speed is not high enough (I am
expecting to be able to run at the highest speed possible, 600 MHz if I am
not wrong)
volatile float sec_init;
volatile float sec_end;
volatile uint32_t cnt;
const uint32_t maxiter = 10000000;
cnt = maxiter;
printf("T\n");
sec_init = second();
while (cnt)
{
cnt--;
asm("");
}
sec_end = second();
printf("P\n");
printf("Time difference for %d iterations: %1.5f secs\n", maxiter, sec_end
- sec_init);
printf("Number of iterations per second: %1.3f\n", (float)(maxiter) /
(sec_end - sec_init));
second() is a function which simply reports back the number of seconds run
since startup, and I know it works properly.
Running above code:
T
P
Time difference for 10000000 iterations: 5.48938 secs
Number of iterations per second: *1821699.375*
(The time 5.48938 secs is correct, using the time stamp feature of TeraTerm
confirms that)
I was expecting something in the range of hundreds of hundreds of millions
of iterations per second.
*How can I configure the MPU on BeagleBoard Rev C to run at the highest
possible frequency?*
Making a dump of the relevant register configurations of PRM and CM
registers does not show any remarkable thing. Indeed, if my understanding
is correct, the MPU clock frequency should be 26 MHz / 2 x 500 / 12 = 541
MHz. But obviously, it is not.
U-Boot 2009.11 (Feb 23 2010 - 15:33:48)
OMAP3530-GP ES3.0, CPU-OPP2 L3-165MHz
OMAP3 Beagle board + LPDDR/NAND
I2C: ready
DRAM: 256 MB
NAND: 256 MiB
*** Warning - bad CRC or NAND, using default environment
In: serial
Out: serial
Err: serial
Board revision C1/C2/C3
Die ID #5760000300000000040323090d007008
Hit any key to stop autoboot: 0
OMAP3 beagleboard.org #
OMAP3 beagleboard.org #
OMAP3 beagleboard.org # loads
## Ready for S-Record download ...
..........................
## First Load Addr = 0x80008000
## Last Load Addr = 0x8001A65B
## Total Size = 0x0001265C = 75356 Bytes
## Start Addr = 0x80008000
OMAP3 beagleboard.org # go 80008000
## Starting application at 0x80008000 ...
[print_clock_info_clock_control] *PRM_CLKSEL: 0x00000003*
[print_clock_info_clock_control] *> SYS_CLKIN_SEL = 0x3*
[print_clock_info_clock_control] *>> OSC_SYS_CLK is 26.0 MHz*
[print_clock_info_clock_control] PRM_CLKSRC_CTRL: 0x00000080
[print_clock_info_clock_control] > CLKOUT_EN = 0x80
[print_clock_info_clock_control] >> sys_clkout1 is enabled
[print_clock_info_clock_pll] CM_CLKEN_PLL: 0x00370037
[print_clock_info_clock_pll] > PWRDN_EMU_PERIPH = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL4_M6X2_CLK HSDIVIDER path
[print_clock_info_clock_pll] > PWRDN_CAM = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL4_M5X2_CLK HSDIVIDER path
[print_clock_info_clock_pll] > PWRDN_DSS1 = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL4_M4X2_CLK HSDIVIDER path
[print_clock_info_clock_pll] > PWRDN_TV = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL4_M3X2_CLK HSDIVIDER path
[print_clock_info_clock_pll] > PWRDN_96M = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL4_M2X2_CLK path
[print_clock_info_clock_pll] > EN_PERIPH_DPLL_LPMODE = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL4 LP mode to re-enter the
normal mode at the following lock or re-lock sequence
[print_clock_info_clock_pll] > PERIPH_DPLL_FREQSEL = 0x3
[print_clock_info_clock_pll] >> Range of the DPLL4 internal frequency
depending on the DPLL reference clock and the N divider: 0.75 MHz - 1.0 MHz
[print_clock_info_clock_pll] > EN_PERIPH_DPLL_DRIFTGUARD = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL4 automatic recalibration
mode
[print_clock_info_clock_pll] > EN_PERIPH_DPLL = 0x7
[print_clock_info_clock_pll] >> Enables the DPLL4 in lock mode
[print_clock_info_clock_pll] > PWRDN_EMU_CORE = 0x0
[print_clock_info_clock_pll] >> Power-up the DPLL3_M3X2 HSDIVIDER path
[print_clock_info_clock_pll] > EN_CORE_DPLL_LPMODE = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL3 LP mode to re-enter the
normal mode at the following lock or re-lock sequence
[print_clock_info_clock_pll] > CORE_DPLL_FREQSEL = 0x3
[print_clock_info_clock_pll] >> Range of the DPLL3 internal frequency
depending on the DPLL reference clock and the N divider: 0.75 MHz - 1.0 MHz
[print_clock_info_clock_pll] > EN_CORE_DPLL_DRIFTGUARD = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL3 automatic recalibration
mode
[print_clock_info_clock_pll] > EN_CORE_DPLL = 0x7
[print_clock_info_clock_pll] >> Enables the DPLL3 in lock mode
[print_clock_info_clock_pll] CM_CLKEN2_PLL: 0x00000011
[print_clock_info_clock_pll] > EN_PERIPH2_DPLL_LPMODE = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL5 LP mode to re-enter the
normal mode at the following lock or re-lock sequenc
[print_clock_info_clock_pll] > PERIPH2_DPLL_FREQSEL = 0x1
[print_clock_info_clock_pll] >> Range of the second PERIPHERAL DPLL
internal frequency depending on the DPLL reference clock and the N divider:
Reserved
[print_clock_info_clock_pll] > EN_PERIPH2_DPLL_DRIFTGUARD = 0x0
[print_clock_info_clock_pll] >> Disables the DPLL5 automatic recalibration
mode
[print_clock_info_clock_pll] > EN_PERIPH2_DPLL = 0x1
[print_clock_info_clock_pll] >> Put the second DPLL5 in low power stop mode
[print_clock_info_clock_pll] CM_IDLEST_CKGEN: 0x00001E3F
[print_clock_info_clock_pll] > ST_EMU_PERIPH_CLK = 0x0
[print_clock_info_clock_pll] >> EMU_PER_ALWON_CLK is not active
[print_clock_info_clock_pll] > ST_CAM_CLK = 0x1
[print_clock_info_clock_pll] >> CAM_MCLK is not active
[print_clock_info_clock_pll] > ST_DSS1_CLK = 0x1
[print_clock_info_clock_pll] >> DSS1_ALWON_FCLK is not active
[print_clock_info_clock_pll] > ST_TV_CLK = 0x1
[print_clock_info_clock_pll] >> DPLL4_M3X2_CLK is not active
[print_clock_info_clock_pll] > ST_FUNC96M_CLK = 0x1
[print_clock_info_clock_pll] >> DPLL4_M2X2_CLK is not active
[print_clock_info_clock_pll] > ST_EMU_CORE_CLK = 0x0
[print_clock_info_clock_pll] >> EMU_CORE_ALWON_CLK is not active
[print_clock_info_clock_pll] > ST_54M_CLK = 0x1
[print_clock_info_clock_pll] >> 54MHz is active
[print_clock_info_clock_pll] > ST_12M_CLK = 0x1
[print_clock_info_clock_pll] >> 12M_FCLK is active
[print_clock_info_clock_pll] > ST_48M_CLK = 0x1
[print_clock_info_clock_pll] >> 48M_FCLK is active
[print_clock_info_clock_pll] > ST_96M_CLK = 0x1
[print_clock_info_clock_pll] >> 96M_FCLK is active
[print_clock_info_clock_pll] > ST_PERIPH_CLK = 0x1
[print_clock_info_clock_pll] >> DPLL4 is locked
[print_clock_info_clock_pll] > ST_CORE_CLK = 0x1
[print_clock_info_clock_pll] >> DPLL3 is locked
[print_clock_info_clock_pll] CM_IDLEST2_CKGEN: 0x00000000
[print_clock_info_clock_pll] > ST_FUNC120M_CLK = 0x0
[print_clock_info_clock_pll] >> DPLL5_M2_CLK is not active
[print_clock_info_clock_pll] > ST_120M_CLK = 0x0
[print_clock_info_clock_pll] >> USB HOST 120M_FCLK is not active
[print_clock_info_clock_pll] > ST_PERIPH2_CLK = 0x0
[print_clock_info_clock_pll] >> DPLL5 is bypassed
[print_clock_info_clock_pll] CM_AUTOIDLE_PLL: 0x00000000
[print_clock_info_clock_pll] > AUTO_PERIPH_DPLL = 0x0
[print_clock_info_clock_pll] >> DPLL4 auto control disabled
[print_clock_info_clock_pll] > AUTO_PERIPH_DPLL = 0x0
[print_clock_info_clock_pll] >> DPLL3 auto control disabled
[print_clock_info_clock_pll] CM_AUTOIDLE2_PLL: 0x00000000
[print_clock_info_clock_pll] > AUTO_PERIPH2_DPLL = 0x0
[print_clock_info_clock_pll] >> DPLL5 auto control disabled
[print_clock_info_clock_pll] CM_CLKSEL1_PLL: 0x094C0C00
[print_clock_info_clock_pll] > CORE_DPLL_CLKOUT_DIV = 0x01
[print_clock_info_clock_pll] >> DPLL3 output clock is divided by 1
[print_clock_info_clock_pll] > CORE_DPLL_MULT = 0x14C
[print_clock_info_clock_pll] >> DPLL3 multiplier factor: 332
[print_clock_info_clock_pll] > CORE_DPLL_DIV = 0x0C
[print_clock_info_clock_pll] >> DPLL3 divider factor: 12
[print_clock_info_clock_pll] > SOURCE_96M = 0x0
[print_clock_info_clock_pll] >> Source for 96M_FCLK is CM_96M_FCLK
[print_clock_info_clock_pll] > SOURCE_54M = 0x0
[print_clock_info_clock_pll] >> Source for 54MHz clock is DPLL4_M3X2_CLK
[print_clock_info_clock_pll] > SOURCE_48M = 0x0
[print_clock_info_clock_pll] >> Source for Func_12M_clk and Func_48M_clk is
CM_96M_FCLK
[print_clock_info_clock_pll] CM_CLKSEL2_PLL: 0x0001B00C
[print_clock_info_clock_pll] > PERIPH_DPLL_MULT = 0x1B0
[print_clock_info_clock_pll] >> DPLL4 multiplier factor: 432
[print_clock_info_clock_pll] > PERIPH_DPLL_DIV = 0x0C
[print_clock_info_clock_pll] >> DPLL4 divider factor: 12
[print_clock_info_clock_pll] CM_CLKSEL3_PLL: 0x00000009
[print_clock_info_clock_pll] > DIV_96M = 0x09
[print_clock_info_clock_pll] >> 96 MHz clock is DPLL4 clock divided by 9
[print_clock_info_clock_pll] CM_CLKSEL4_PLL: 0x00000000
[print_clock_info_clock_pll] > PERIPH2_DPLL_MULT = 0x000
[print_clock_info_clock_pll] >> DPLL5 multiplier factor: 0
[print_clock_info_clock_pll] > PERIPH2_DPLL_DIV = 0x00
[print_clock_info_clock_pll] >> DPLL5 divider factor: 0
[print_clock_info_clock_pll] CM_CLKSEL5_PLL: 0x00000001
[print_clock_info_clock_pll] > DIV_120M = 0x01
[print_clock_info_clock_pll] >> 120 MHz clock is DPLL5 clock divided by 1
[print_clock_info_clock_pll] CM_CLKOUT_CTRL: 0x00000003
[print_clock_info_clock_pll] > CLKOUT2_EN = 0x0
[print_clock_info_clock_pll] >> sys_clkout2 is disabled
[print_clock_info_clock_pll] > CLKOUT2_DIV = 0x0
[print_clock_info_clock_pll] >> sys_clkout2 / 1
[print_clock_info_clock_pll] > CLKOUT2_DIV = 0x3
[print_clock_info_clock_pll] >> sys_clkout2 source is 54 MHz clock
[print_clock_info_clk_mpu] *CM_CLKEN_PLL_MPU: 0x00000037*
[print_clock_info_clk_mpu] > EN_MPU_DPLL_LPMODE = 0x0
[print_clock_info_clk_mpu] >> Disables the MPU DPLL LP mode to re-enter the
normal mode at the following lock or re-lock sequence
[print_clock_info_clk_mpu] > MPU_DPLL_FREQSEL = 0x3
[print_clock_info_clk_mpu] >> Range of the DPLL1 internal frequency
depending on the DPLL reference clock and the N divider: 0.75 MHz - 1.0 MHz
[print_clock_info_clk_mpu] > EN_MPU_DPLL_DRIFTGUARD = 0x0
[print_clock_info_clk_mpu] >> Disables the DPLL1 automatic recalibration
mode
[print_clock_info_clk_mpu] *> EN_MPU_DPLL = 0x7*
[print_clock_info_clk_mpu] *>> Enables the DPLL1 in lock mode*
[print_clock_info_clk_mpu] *CM_IDLEST_MPU: 0x00000000*
[print_clock_info_clk_mpu] *> ST_MPU = 0x0*
[print_clock_info_clk_mpu] *>> MPU is active*
[print_clock_info_clk_mpu] *CM_IDLEST_PLL_MPU: 0x00000001*
[print_clock_info_clk_mpu] *> ST_MPU_CLK = 0x1*
[print_clock_info_clk_mpu] *>> DPLL1 is locked*
[print_clock_info_clk_mpu] CM_AUTOIDLE_PLL_MPU: 0x00000000
[print_clock_info_clk_mpu] > AUTO_MPU_DPLL = 0x0
[print_clock_info_clk_mpu] >> DPLL1 auto control disabled
[print_clock_info_clk_mpu] *CM_CLKSEL1_PLL_MPU: 0x0011F40C*
[print_clock_info_clk_mpu] *> MPU_CLK_SRC = 0x02*
[print_clock_info_clk_mpu] *>> DPLL1_FCLK is CORE_CLK divided by 2*
[print_clock_info_clk_mpu] *> MPU_DPLL_MULT = 0x1F4*
[print_clock_info_clk_mpu] *>> DPLL1 multiplier factor: 500*
[print_clock_info_clk_mpu] *> MPU_DPLL_DIV = 0x0C*
[print_clock_info_clk_mpu] *>> DPLL1 divider factor: 12*
[print_clock_info_clk_mpu] *CM_CLKSEL2_PLL_MPU: 0x00000001*
[print_clock_info_clk_mpu] *> MPU_DPLL_CLKOUT_DIV = 0x01*
[print_clock_info_clk_mpu] *>> DPLL1 CLKOUTX2 divided by 1*
[print_clock_info_clk_mpu] CM_CLKSTCTRL_MPU: 0x00000000
[print_clock_info_clk_mpu] > CLKTRCTRL_MPU = 0x00
[print_clock_info_clk_mpu] >> Automatic clock state transition of the MPU
domain is disabled
[print_clock_info_clk_mpu] *CM_CLKSTST_MPU: 0x00000001*
[print_clock_info_clk_mpu] *> CLKACTIVITY_MPU = 0x1*
[print_clock_info_clk_mpu] *>> MPU domain clock is active*
--
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