Thanks, good catch! A question though: Under what circumstances would the 
ADC not start? I've been running the ADC now and have not had a startup 
fail.

On Friday, September 23, 2016 at 7:57:06 AM UTC-5, TJF wrote:
>
> Hi Phil!
>
> Your code is incomplete. The error handling is missing, for the case that 
> the ADC subsystem doesn't come up. Your code just continues.
>
> Am Mittwoch, 21. September 2016 18:13:59 UTC+2 schrieb Phil:
>>
>> *PRU Code*
>> //--------------------------------------------------------------------
>> // Enable and/or turn on hardware
>> // Code in this section must be ordered as listed for proper
>> // hardware startup.
>>
>>         // Enable OCP
>>         lbco    r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
>>         clr     r0, 4
>>         sbco    r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
>>
>>         // Enable ADC clock, wait for ADC module to start before 
>> proceeding
>>         mov     r0, CM_WKUP_base + CM_WKUP_ADC_TSC_CLKCTRL
>>         mov     r1, 2
>>         sbbo    r1, r0, 0, 4
>>         mov     r1, 0                           // clear timeout counter
>> AdcWait:
>>         LBBO    r0, adc_base, ADC_REVISION, 4   // load ADC REVISION
>>         QBNE    AdcUp, r0, 0                    // exit if ADC is running
>>         ADD     r1, r1, 1                       // increase timeout 
>> counter
>>         QBGE    AdcWait, r1.b1, 16              // if no timeout -> wait
>> AdcUp:
>>
>> //--------------------------------------------------------------------
>>
>
> But it needs something like
>
> ...
>
>         QBGE    AdcWait, r1.b1, 16              // if no timeout -> wait
>
>         SBCO    r1, DRam, 0, 4                  // store timeout counter 
> in DRam
>         HALT                                    // stop PRU, since ADC 
> isn't ready
> AdcUp:
> ...
>
> Regards
>  
>

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