The System Reference Manual (SRM) says you're supposed to gate all GPIO
(and other inputs) such that they aren't driven until either the SYS_RESET
line goes high (according to SRM section 7.1, 8.0, and possibly others) or
until the VDD_3V3B rail is up (according to SRM 8.6.2). Are these conditions
identical in practice? If not which is the right one?
Is there a good tested way (appropriate IC I guess) to gate such signals?
Also, the reference manual section 8.3.1 says this:
If you plan to use any of these signals, then on power up, these pins
should not be driven. If you do, it can affect the boot mode of the
processor and could keep the processor from booting or working correctly.
while not wrong this paragraph is going to create a dangerous wrong impression
for most readers: that the boot pins are special and are the ones you have to
worry about driving early. I think it would be good to change this paragraph
or add a pointer to the other warnings that apply to all pins or something.
Finally, section 8.6.2 says this:
3) Do not apply any voltages that are generated from external sources.
which if the ground is common and solid and the voltage source is behaving
I can't believe. Can someone explain how the bone can tell the difference
in this case? Is it so sensitive that any tiny ground flow can fry things
or what?
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