>>>>> "Steven" == Steven Critchfield <[EMAIL PROTECTED]> writes:
Steven> As I understand the PCI spec, there are 4 interrupt lines Steven> called A,B,C, and D. In slot 1, They appear in that order. In Steven> slot 2 they shift, in slot 3 they shift and again in slot 4. That is correct, except that all top-shelf systems use multiple pci busses to spread both the interrupt and the bandwidth load. This is especially true of systems with the pci-x slots. Pci-express I believe takes that one further and uses a switch and serial links, doing for the expansion cards what 10-baseT did for ethernet. At that point -- especially on the opteron and the 64bit xeons -- the pics *should* be wired so there is no sharing. Whether even such a box as that can deal well with, say, seven cards generating 1 kHz of ints, plus the timer doing so (2.6 kernels use HZ=1000 internally on x86 & x86-64, even though it looks like 100 from userspace to maintain compatability with older utils) and however many ints the network and disk interfaces generate is a question left to answer. (Why seven? 7 x 4(DS1) == DS3.) At some point, of course, it will be necessary to do what routers do: switch from interrupts to polling when the load is high enough. -JimC _______________________________________________ Asterisk-Users mailing list [EMAIL PROTECTED] http://lists.digium.com/mailman/listinfo/asterisk-users To UNSUBSCRIBE or update options visit: http://lists.digium.com/mailman/listinfo/asterisk-users
