Hi, Check at the end of right column at page 2 of pointed manual: "... Two forms of over-voltage protection are provided, one that permits 5V compliance, and one that does not. For 5V compliance, a zener-like structure connected to ground turns on when the output rises to approximately 6.5V. When 5V compliance is not required, a conventional clamp diode may be connected to the output supply voltage, Vcco. The type of over-voltage protection can be selected independently for each pad".
As you pointed (and the same page 2 says too), both 3.3V and 5V PCI uses the same Vcco voltage, 3.3V, but as you can see at pages 31-35, Xilinx have different symbols for input/output buffers for each pad: - IBUF_PCI33_3 or IBUF_PCI33_5 or IBUF_PCI66_3; - IBUFG_PCI33_3 or IBUFG_PCI33_5 or IBUFG_PCI66_3; - OBUF_PCI33_3 or OBUF_PCI33_5 or OBUF_PCI66_3; - OBUFT_PCI33_3 or OBUFT_PCI33_5 or OBUFT_PCI66_3; - IOBUF_PCI33_3 or IOBUF_PCI33_5 or IOBUF_PCI66_3; Page 43 specifies that for PCI33_3 and PCI66_3 maximum input voltage at pad is Vcco+0.5V, i.e. 3.8V (uses clamp diode to Vcco), but for PCI33_5 there is 5.5V (uses zener diode to ground). As for TTL specification, "0" voltage must be between 0 and 0.8V, and "1" voltage must be between 2.4 and 5V, so LVTTL (3.3V)with their levels must comply with TTL spec. So, I don't see any is no problem if you connect zener-protected pins (5V tolerant) to 3.3V system. There was for Xilinx. But what about PEF? As I see for one used for TE410P (to remember - I don't have TE405P to check which chips used for it), there was 3.3V-only chips, so IMHO TE405P must have any sort of 3.3V source (from onboard regulator or from PCI connector). Any way, I don't see any problems to connect TE405P to 3.3V bus (after making second, 3.3V, key hole). But I'm not Digium's hardware engineer... ;-)' I think there would be dual-voltage TE405P+ cards (TE405P with two key holes) available when all TE410P "already-made" will be sold out. ;-)' WBR, Paul. ----- Original Message ----- From: "Andrew Kohlsmith" <[EMAIL PROTECTED]> To: <[EMAIL PROTECTED]> Sent: Wednesday, April 14, 2004 2:05 AM Subject: Re: [Asterisk-Dev] TE405P *hardware* question > Thanks for the reply. > > > As I checked out Xilinx's datasheets CPLD used for TE410P's PCI bridge is > > Spartan II-E family which is maximum 3.3V capable, while regular Spartan-II > > family (which is, I think, used for TE405P) is supports both 3.3 and 5V for > > I/O pins, but requires different termination for each voltage. I don't have > > TE405P, but as I remember there was a sort of problems with some chipsets. > > May be TE410P have ones too but they are not reproducible because "ugly" > > chipset (or motherboard vendors) isn't support 3.3V for this chipset. > > http://direct.xilinx.com/bvdocs/publications/ds001_2.pdf > > Page 30 says that it can indeed use 3.3V or 5V for PCI, and that the clamps > need to be different for 5V tolerant systems (which the TE405P is), so that > much should work... > > The next page goes on to say that the standard doesn't require use of Vref of > board term voltage, only 3.3V on Vcco. Now it goes on to say that I/O > configured for PCI 33MHz 5V standard are also 5V tolerant... we know all > that since the card is a 5V card. :-) > > Page 43 gives the PCI 3V and 5V buffer Voltage specifications -- it looks like > there should be no issues whatsoever, I believe that the Vih/il and Voh/ol > specs are acceptable for both 3V and 5V systems. Vcco does not change for 5V > or 3V operation. > > The pinout tables are a little confusing for me, but with the information > gathered so far there shouldn't be any obvious problem with sawing the key > out for 3V operation. I would still like to hear from Digium as to whether > the IOREF is connected to the correct place on the PCI connector, and what > the unstuffed voltage regulator was to be used for and its part number. > > Regards, > Andrew > > > > > > So, I think, the problem is different termination of I/O blocks at the > > Xilinx for 3.3 and 5 V for Spartan-II family. > > > > > > WBR, > > Paul. > > > > > > ----- Original Message ----- > > From: "Andrew Kohlsmith" <[EMAIL PROTECTED]> > > To: <[EMAIL PROTECTED]> > > Sent: Tuesday, April 13, 2004 11:24 PM > > Subject: [Asterisk-Dev] TE405P *hardware* question > > > > > Is there a specific design issue with making the TE405P a universal > > > 3.3V/5V product? I've done a cursory review of the Xilinx part and it > > > seems that it should be just fine to plug in to a 3V or 5V PCI slot, if I > > > take a hacksaw and create the appropriate key. > > > > > > I haven't yet traced out the VIO pins to make sure that the Spartan will > > > honour the PCI bus voltage. > > > > > > Yes I am almost willing to sacrifice a $1500 card at this point in time. > > > :-) > > > > > > Can anyone who is familliar with the hardware design of this product > > > explain why there are separate 3V and 5V cards? Hell even the X101P and > > > TDM400P are dual-voltage capable, what is preventing it on the quad T1/E1 > > > cards? > > > > > > Regards, > > > Andrew > > > _______________________________________________ > > > Asterisk-Dev mailing list > > > [EMAIL PROTECTED] > > > http://lists.digium.com/mailman/listinfo/asterisk-dev > > > To UNSUBSCRIBE or update options visit: > > > http://lists.digium.com/mailman/listinfo/asterisk-dev > > > > _______________________________________________ > > Asterisk-Dev mailing list > > [EMAIL PROTECTED] > > http://lists.digium.com/mailman/listinfo/asterisk-dev > > To UNSUBSCRIBE or update options visit: > > http://lists.digium.com/mailman/listinfo/asterisk-dev > _______________________________________________ > Asterisk-Dev mailing list > [EMAIL PROTECTED] > http://lists.digium.com/mailman/listinfo/asterisk-dev > To UNSUBSCRIBE or update options visit: > http://lists.digium.com/mailman/listinfo/asterisk-dev > _______________________________________________ Asterisk-Dev mailing list [EMAIL PROTECTED] http://lists.digium.com/mailman/listinfo/asterisk-dev To UNSUBSCRIBE or update options visit: http://lists.digium.com/mailman/listinfo/asterisk-dev
