My sense is that a LOT of the instructions being added with each new hardware generation are coming from the HLL code optimization teams (particularly Java and C/C++) and mainly from the increasingly critical need to execute ported open-source code with ever-higher levels of performance.
I could be totally wrong of course, but that's what I see. Peter -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Martin Trübner Sent: Tuesday, November 15, 2022 10:38 AM To: [email protected] Subject: Re: ADD LOGICAL WITH SIGNED IMMEDIATE HIGH N to increase a register without setting the condition code beyond what LA can do. Prettty sure that some developer within(!) IBM stumbled over some coding in a macro (or module) that needed adaption to situations where more than 4095 is needed (LA R,inc(,R)) or a negative value. Martin Am 15.11.22 um 16:32 schrieb Ian Worthington: > I noticed today that > ALSIH R1,I2 > > has a partner-in-crime > > ALSIHN R1,I2 > > which differs only, as far as I can tell, in that the later does not set the > condition code. > I'm curious what the need was for a distinct instruction to do the second. > Anyone know? > > > > Best wishes / Mejores deseos / Meilleurs vœux > > Ian ... This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
