Hi, I am trying H616 support patch on Orange Pi Zero 2.
Current U-boot (2023.04) device tree connects AXP305 to RSB bus
(not I2C) and kernel detects it successfully.
USB is still not working. DW-APB's UART fix is already applied,
console is working.
----
U-Boot SPL 2023.04 (May 16 2023 - 20:38:03 +0900)
DRAM: 1024 MiB
Trying to boot from MMC1
NOTICE: BL31: lts-v2.8.4(debug):
NOTICE: BL31: Built : 19:29:55, Apr 22 2023
NOTICE: BL31: Detected Allwinner H616 SoC (1823)
NOTICE: BL31: Found U-Boot DTB at 0x4a096e98, model: OrangePi Zero2
INFO: ARM GICv2 driver initialized
INFO: Configuring SPC Controller
INFO: PMIC: Probing AXP305 on RSB
INFO: PMIC: aldo1 voltage: 3.300V
INFO: PMIC: aldo2 voltage: 3.300V
INFO: PMIC: aldo3 voltage: 3.300V
INFO: PMIC: bldo1 voltage: 1.800V
INFO: PMIC: dcdcd voltage: 1.500V
INFO: PMIC: dcdce voltage: 3.300V
INFO: BL31: Platform setup done
INFO: BL31: Initializing CPU workaround for 855873 was applied
INFO: BL31: cortex_a53: CPU workaround for 1530924 was applied
INFO: PSCI: Suspend is unavailable
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x4a000000
INFO: SPSR = 0x3c9
INFO: Changed devicetree.
U-Boot 2023.04 (May 16 2023 - 20:38:03 +0900) Allwinner Technology
CPU: Allwinner H616 (SUN50I)
Model: OrangePi Zero2
DRAM: 1 GiB
Core: 48 devices, 18 uclasses, devicetree: separate
WDT: Not starting watchdog@30090a0
MMC:mmc@4020000: 0
Loading EnvironmUnable to read "uboot.env" from mmc0:1...
In: serial@5000000
Out: serial@5000000
Err: serial@5000000
Net: eth0: ethernet@5020000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
20192 bytes read in 5 ms (3.9 MiB/s)
Working FDT set to 4fa00000
No EFI system partition
No EFI system partition
Failed to persist EFI variables
BootOrder not defined
EFI boot manager: Cannot load any image
Found EFI removable media binary efi/boot/bootaa64.efi
219050 bytes read in 12 ms (17.4 MiB/s)
Working FDT set to 4fa00000
Booting /efi\boot\bootaa64.efi
disks: sd0*
>> OpenBSD/arm64 BOOTAA64 1.18
boot>
cannot open sd0a:/etc/random.seed: No such file or directory
booting sd0a:/bsd: 2843208+1071676+12723936+634664
[1695524+785640+168+266603]=0x155c8b0
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2023 OpenBSD. All rights reserved. https://www.OpenBSD.org
OpenBSD 7.3-current (RAMDISK) #31: Tue May 16 20:37:02 JST 2023
[email protected]:/usr/src/sys/arch/arm64/compile/RAMDISK
real mem = 1072021504 (1022MB)
avail mem = 1000796160 (954MB)
random: boothowto does not indicate good seed
mainbus0 at root: OrangePi Zero2
psci0 at mainbus0: PSCI 1.1, SMCCC 1.2
cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
cpu0: 32KB 64b/line 2-way L1 VIPT I-cac6-way L2 cache
cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16
efi0 at mainbus0: UEFI 2.10
efi0: Das U-Boot rev 0x20230400
smbios0 at efi0: SMBIOS 3.0
smbios0: vendor U-Boot version "2023.04" date 04/01/2023
smbios0: Unknown Unknown Product
"osc24M-clk" at mainbus0 not configured
"pmu" at mainbus0 not configured
agtimer0 at mainbus0: 24000 kHz
simplebus0 at mainbus0: "soc"
sxisyscon0 at simplebus0
sxiccmu0 at simplebus0
sxipio0 at simplebus0: 85 pins
ampintc0 at simplebus0 nirq 192, ncpu 4: "interrupt-controller"
sxiccmu1 at simplebus0
sxipio1 at simplebus0: 2 pins
sxirsb0 at simplebus0
axppmic0 at sxirsb0 addr 0x745: AXP305
sxidog0 at simplebus0
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
com0 at simplebus0: dw16550
com0: console
"spi" at simplebus0 not configured
dwxe0 at simplebus0: address 02:00:fc:bc:f9:89
rgephy0 at dwxe0 phy 1: RTL8169S/8110S/8211 PHY, rev. 6
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00
addr 1
ohci0 at simplebus0: version 1.0
"rtc" at simplebus0 not configured
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio0: 32 pins
gpio8 at sxipio0: 32 pins
gpio9 at sxipio1: 32 pins
usb1 at ohci0: USB revision 1.0
uhub1 at usb1 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00
addr 1
"leds" at mainbus0 not configured
"vcc5v" at mainbus0 not configured
"regulator-usb1-vbus" at mainbus0 not configured
"binman" at mainbus0 not configured
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <Apacer, SD16G, 0030> removable
sd0: 14768MB, 512 bytes/sector, 30244864 sectors
softraid0 at root
scsibus1 at softraid0: 256 targets
root on rd0a swap on rd0b dump on rd0b
WARNING: CHECK AND RESET THE DATE!
erase ^?, werase ^W, kill ^U, intr ^C, status ^T
Welcome to the OpenBSD/arm64 7.3 installation program.
(I)nstall, (U)pgrade, (A)utoinstall or (S)hell?
----
patch is nothing different with previous mail, repost.
----
Index: axppmic.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/axppmic.c,v
retrieving revision 1.16
diff -u -p -r1.16 axppmic.c
--- axppmic.c 3 Sep 2022 18:05:10 -0000 1.16
+++ axppmic.c 16 May 2023 12:37:56 -0000
@@ -306,6 +306,7 @@ const struct axppmic_device axppmic_devi
{ "x-powers,axp209", "AXP209", axp209_regdata, axp209_sensdata },
{ "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata },
{ "x-powers,axp223", "AXP223", axp221_regdata, axp221_sensdata },
+ { "x-powers,axp305", "AXP305", axp806_regdata },
{ "x-powers,axp803", "AXP803", axp803_regdata, axp803_sensdata },
{ "x-powers,axp805", "AXP805", axp806_regdata },
{ "x-powers,axp806", "AXP806", axp806_regdata },
@@ -511,7 +512,8 @@ axppmic_attach_common(struct axppmic_sof
sc->sc_sensdata = device->sensdata;
/* Switch AXP806 into master or slave mode. */
- if (strcmp(name, "x-powers,axp805") == 0 ||
+ if (strcmp(name, "x-powers,axp305") == 0 ||
+ strcmp(name, "x-powers,axp805") == 0 ||
strcmp(name, "x-powers,axp806") == 0) {
if (OF_getproplen(node, "x-powers,master-mode") == 0 ||
OF_getproplen(node, "x-powers,self-working-mode") == 0) {
Index: ehci_fdt.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/ehci_fdt.c,v
retrieving revision 1.10
diff -u -p -r1.10 ehci_fdt.c
--- ehci_fdt.c 3 Apr 2023 01:57:41 -0000 1.10
+++ ehci_fdt.c 16 May 2023 12:37:56 -0000
@@ -206,6 +206,7 @@ struct ehci_phy ehci_phys[] = {
{ "allwinner,sun8i-r40-usb-phy", sun4i_phy_init },
{ "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init },
{ "allwinner,sun50i-h6-usb-phy", sun4i_phy_init },
+ { "allwinner,sun50i-h616-usb-phy", sun4i_phy_init },
{ "allwinner,sun50i-a64-usb-phy", sun4i_phy_init },
{ "allwinner,sun9i-a80-usb-phy", sun9i_phy_init },
};
@@ -313,6 +314,13 @@ sun4i_phy_init(struct ehci_fdt_softc *sc
OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) {
val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
val &= ~(1 << 1);
+ bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
+ }
+ if (OF_is_compatible(node, "allwinner,sun50i-h616-usb-phy") ||
+ OF_is_compatible(node, "allwinner,sun50i-a83t-usb-phy")) {
+ val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
+ val |= 1 << 5; /* set VBUSVLDEXT */
+ val &= ~(1 << 3); /* clear SIDDQ */
bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
}
Index: sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.31
diff -u -p -r1.31 sxiccmu.c
--- sxiccmu.c 28 Jun 2022 23:43:12 -0000 1.31
+++ sxiccmu.c 16 May 2023 12:37:56 -0000
@@ -104,6 +104,9 @@ uint32_t sxiccmu_h3_r_get_frequency(stru
uint32_t sxiccmu_h6_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_h6_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_h6_r_get_frequency(struct sxiccmu_softc *, uint32_t);
+uint32_t sxiccmu_h616_get_frequency(struct sxiccmu_softc *, uint32_t);
+int sxiccmu_h616_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *, uint32_t);
uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
@@ -149,7 +152,9 @@ sxiccmu_match(struct device *parent, voi
OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-h6-ccu") ||
- OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu"));
+ OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu"));
}
void
@@ -276,6 +281,22 @@ sxiccmu_attach(struct device *parent, st
sc->sc_nresets = nitems(sun50i_h6_r_resets);
sc->sc_get_frequency = sxiccmu_h6_r_get_frequency;
sc->sc_set_frequency = sxiccmu_nop_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h616-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h616_gates;
+ sc->sc_ngates = nitems(sun50i_h616_gates);
+ sc->sc_resets = sun50i_h616_resets;
+ sc->sc_nresets = nitems(sun50i_h616_resets);
+ sc->sc_get_frequency = sxiccmu_h616_get_frequency;
+ sc->sc_set_frequency = sxiccmu_h616_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h616_r_gates;
+ sc->sc_ngates = nitems(sun50i_h616_r_gates);
+ sc->sc_resets = sun50i_h616_r_resets;
+ sc->sc_nresets = nitems(sun50i_h616_r_resets);
+ sc->sc_get_frequency = sxiccmu_h616_r_get_frequency;
+ sc->sc_set_frequency = sxiccmu_nop_set_frequency;
} else {
for (node = OF_child(node); node; node = OF_peer(node))
sxiccmu_attach_clock(sc, node, faa->fa_nreg);
@@ -1338,7 +1359,6 @@ sxiccmu_h6_get_frequency(struct sxiccmu_
case H6_CLK_APB2:
/* XXX Controlled by a MUX. */
return 24000000;
- break;
}
printf("%s: 0x%08x\n", __func__, idx);
@@ -1352,7 +1372,52 @@ sxiccmu_h6_r_get_frequency(struct sxiccm
case H6_R_CLK_APB2:
/* XXX Controlled by a MUX. */
return 24000000;
- break;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+/* Allwinner H616 */
+#define H616_AHB3_CFG_REG 0x051c
+#define H616_AHB3_CLK_FACTOR_N(x) (((x) >> 8) & 0x3)
+#define H616_AHB3_CLK_FACTOR_M(x) (((x) >> 0) & 0x3)
+
+uint32_t
+sxiccmu_h616_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ uint32_t reg, m, n;
+ uint32_t freq;
+
+ switch (idx) {
+ case H616_CLK_PLL_PERIPH0:
+ /* Not hardcoded, but recommended. */
+ return 600000000;
+ case H616_CLK_PLL_PERIPH0_2X:
+ return sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0) * 2;
+ case H616_CLK_AHB3:
+ reg = SXIREAD4(sc, H616_AHB3_CFG_REG);
+ /* assume PLL_PERIPH0 source */
+ freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0);
+ m = H616_AHB3_CLK_FACTOR_M(reg) + 1;
+ n = 1 << H616_AHB3_CLK_FACTOR_N(reg);
+ return freq / (m * n);
+ case H616_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
+sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ switch (idx) {
+ case H616_R_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
}
printf("%s: 0x%08x\n", __func__, idx);
@@ -1732,9 +1797,8 @@ sxiccmu_h3_set_frequency(struct sxiccmu_
int
sxiccmu_h6_mmc_set_frequency(struct sxiccmu_softc *sc, bus_size_t offset,
- uint32_t freq)
+ uint32_t freq, uint32_t parent_freq)
{
- uint32_t parent_freq;
uint32_t reg, m, n;
uint32_t clk_src;
@@ -1750,8 +1814,6 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
case 52000000:
n = 0, m = 0;
clk_src = H6_SMHC_CLK_SRC_SEL_PLL_PERIPH0_2X;
- parent_freq =
- sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
while ((parent_freq / (1 << n) / 16) > freq)
n++;
while ((parent_freq / (1 << n) / (m + 1)) > freq)
@@ -1776,13 +1838,47 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
int
sxiccmu_h6_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
{
+ uint32_t parent_freq;
+
+ parent_freq = sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
+
switch (idx) {
case H6_CLK_MMC0:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG,
+ freq, parent_freq);
case H6_CLK_MMC1:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG,
+ freq, parent_freq);
case H6_CLK_MMC2:
- return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG, freq);
+ return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG,
+ freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+#define H616_SMHC0_CLK_REG 0x0830
+#define H616_SMHC1_CLK_REG 0x0834
+#define H616_SMHC2_CLK_REG 0x0838
+
+int
+sxiccmu_h616_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t
freq)
+{
+ uint32_t parent_freq;
+
+ parent_freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0_2X);
+
+ switch (idx) {
+ case H616_CLK_MMC0:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC0_CLK_REG,
+ freq, parent_freq);
+ case H616_CLK_MMC1:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC1_CLK_REG,
+ freq, parent_freq);
+ case H616_CLK_MMC2:
+ return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC2_CLK_REG,
+ freq, parent_freq);
}
printf("%s: 0x%08x\n", __func__, idx);
Index: sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.33
diff -u -p -r1.33 sxiccmu_clocks.h
--- sxiccmu_clocks.h 28 Jun 2022 23:43:12 -0000 1.33
+++ sxiccmu_clocks.h 16 May 2023 12:37:56 -0000
@@ -468,6 +468,100 @@ const struct sxiccmu_ccu_bit sun50i_h6_r
[H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 },
};
+/* H616 */
+
+#define H616_CLK_PLL_PERIPH0 4
+#define H616_CLK_PLL_PERIPH0_2X 5
+#define H616_CLK_AHB3 25
+#define H616_CLK_APB1 26
+#define H616_CLK_APB2 27
+#define H616_CLK_MMC0 60
+#define H616_CLK_MMC1 61
+#define H616_CLK_MMC2 62
+#define H616_CLK_BUS_MMC0 63
+#define H616_CLK_BUS_MMC1 64
+#define H616_CLK_BUS_MMC2 65
+#define H616_CLK_BUS_UART0 66
+#define H616_CLK_BUS_UART1 67
+#define H616_CLK_BUS_UART2 68
+#define H616_CLK_BUS_UART3 69
+#define H616_CLK_BUS_UART4 70
+#define H616_CLK_BUS_UART5 71
+#define H616_CLK_BUS_I2C0 72
+#define H616_CLK_BUS_I2C1 73
+#define H616_CLK_BUS_I2C2 74
+#define H616_CLK_BUS_I2C3 75
+#define H616_CLK_BUS_I2C4 76
+#define H616_CLK_BUS_EMAC0 82
+#define H616_CLK_BUS_EMAC1 83
+#define H616_CLK_USB_OHCI0 96
+#define H616_CLK_USB_PHY0 97
+#define H616_CLK_USB_OHCI1 98
+#define H616_CLK_USB_PHY1 99
+#define H616_CLK_USB_OHCI2 100
+#define H616_CLK_USB_PHY2 101
+#define H616_CLK_USB_OHCI3 102
+#define H616_CLK_USB_PHY3 103
+#define H616_CLK_BUS_OHCI0 104
+#define H616_CLK_BUS_OHCI1 105
+#define H616_CLK_BUS_OHCI2 106
+#define H616_CLK_BUS_OHCI3 107
+#define H616_CLK_BUS_EHCI0 108
+#define H616_CLK_BUS_EHCI1 109
+#define H616_CLK_BUS_EHCI2 110
+#define H616_CLK_BUS_EHCI3 111
+
+struct sxiccmu_ccu_bit sun50i_h616_gates[] = {
+ [H616_CLK_PLL_PERIPH0] = { 0x0020, 31 },
+ [H616_CLK_APB1] = { 0xffff, 0xff },
+ [H616_CLK_MMC0] = { 0x0830, 31 },
+ [H616_CLK_MMC1] = { 0x0834, 31 },
+ [H616_CLK_MMC2] = { 0x0838, 31 },
+ [H616_CLK_BUS_MMC0] = { 0x084c, 0 },
+ [H616_CLK_BUS_MMC1] = { 0x084c, 1 },
+ [H616_CLK_BUS_MMC2] = { 0x084c, 2 },
+ [H616_CLK_BUS_UART0] = { 0x090c, 0, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART1] = { 0x090c, 1, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART2] = { 0x090c, 2, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART3] = { 0x090c, 3, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART4] = { 0x090c, 4, H616_CLK_APB2 },
+ [H616_CLK_BUS_UART5] = { 0x090c, 5, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C0] = { 0x091c, 0, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C1] = { 0x091c, 1, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C2] = { 0x091c, 2, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C3] = { 0x091c, 3, H616_CLK_APB2 },
+ [H616_CLK_BUS_I2C4] = { 0x091c, 4, H616_CLK_APB2 },
+ [H616_CLK_BUS_EMAC0] = { 0x097c, 0, H616_CLK_AHB3 },
+ [H616_CLK_BUS_EMAC1] = { 0x097c, 1, H616_CLK_AHB3 },
+ [H616_CLK_USB_OHCI0] = { 0x0a70, 31 },
+ [H616_CLK_USB_PHY0] = { 0x0a70, 29 },
+ [H616_CLK_USB_OHCI1] = { 0x0a74, 31 },
+ [H616_CLK_USB_PHY1] = { 0x0a74, 29 },
+ [H616_CLK_USB_OHCI2] = { 0x0a78, 31 },
+ [H616_CLK_USB_PHY2] = { 0x0a78, 29 },
+ [H616_CLK_USB_OHCI3] = { 0x0a7c, 31 },
+ [H616_CLK_USB_PHY3] = { 0x0a7c, 29 },
+ [H616_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
+ [H616_CLK_BUS_OHCI1] = { 0x0a8c, 1 },
+ [H616_CLK_BUS_OHCI2] = { 0x0a8c, 2 },
+ [H616_CLK_BUS_OHCI3] = { 0x0a8c, 3 },
+ [H616_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
+ [H616_CLK_BUS_EHCI1] = { 0x0a8c, 5 },
+ [H616_CLK_BUS_EHCI2] = { 0x0a8c, 6 },
+ [H616_CLK_BUS_EHCI3] = { 0x0a8c, 7 },
+};
+
+#define H616_R_CLK_APB1 2
+#define H616_R_CLK_APB2 3
+#define H616_R_CLK_APB2_I2C 8
+#define H616_R_CLK_APB2_RSB 13
+
+struct sxiccmu_ccu_bit sun50i_h616_r_gates[] = {
+ [H616_R_CLK_APB1] = { 0xffff, 0xff },
+ [H616_R_CLK_APB2_I2C] = { 0x019c, 0, H616_R_CLK_APB2 },
+ [H616_R_CLK_APB2_RSB] = { 0x01bc, 0, H616_R_CLK_APB2 },
+};
+
/* R40 */
#define R40_CLK_PLL_PERIPH0 11
@@ -877,6 +971,76 @@ const struct sxiccmu_ccu_bit sun50i_h6_r
const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
[H6_R_RST_APB2_I2C] = { 0x019c, 16 },
[H6_R_RST_APB2_RSB] = { 0x01bc, 16 },
+};
+
+/* H616 */
+
+#define H616_RST_BUS_MMC0 14
+#define H616_RST_BUS_MMC1 15
+#define H616_RST_BUS_MMC2 16
+#define H616_RST_BUS_UART0 17
+#define H616_RST_BUS_UART1 18
+#define H616_RST_BUS_UART2 19
+#define H616_RST_BUS_UART3 20
+#define H616_RST_BUS_UART4 21
+#define H616_RST_BUS_UART5 22
+#define H616_RST_BUS_I2C0 23
+#define H616_RST_BUS_I2C1 24
+#define H616_RST_BUS_I2C2 25
+#define H616_RST_BUS_I2C3 26
+#define H616_RST_BUS_I2C4 27
+#define H616_RST_BUS_EMAC0 30
+#define H616_RST_BUS_EMAC1 31
+#define H616_RST_USB_PHY0 38
+#define H616_RST_USB_PHY1 39
+#define H616_RST_USB_PHY2 40
+#define H616_RST_USB_PHY3 41
+#define H616_RST_BUS_OHCI0 42
+#define H616_RST_BUS_OHCI1 43
+#define H616_RST_BUS_OHCI2 44
+#define H616_RST_BUS_OHCI3 45
+#define H616_RST_BUS_EHCI0 46
+#define H616_RST_BUS_EHCI1 47
+#define H616_RST_BUS_EHCI2 48
+#define H616_RST_BUS_EHCI3 49
+
+struct sxiccmu_ccu_bit sun50i_h616_resets[] = {
+ [H616_RST_BUS_MMC0] = { 0x084c, 16 },
+ [H616_RST_BUS_MMC1] = { 0x084c, 17 },
+ [H616_RST_BUS_MMC2] = { 0x084c, 18 },
+ [H616_RST_BUS_UART0] = { 0x090c, 16 },
+ [H616_RST_BUS_UART1] = { 0x090c, 17 },
+ [H616_RST_BUS_UART2] = { 0x090c, 18 },
+ [H616_RST_BUS_UART3] = { 0x090c, 19 },
+ [H616_RST_BUS_UART4] = { 0x090c, 20 },
+ [H616_RST_BUS_UART5] = { 0x090c, 21 },
+ [H616_RST_BUS_I2C0] = { 0x091c, 16 },
+ [H616_RST_BUS_I2C1] = { 0x091c, 17 },
+ [H616_RST_BUS_I2C2] = { 0x091c, 18 },
+ [H616_RST_BUS_I2C3] = { 0x091c, 19 },
+ [H616_RST_BUS_I2C4] = { 0x091c, 20 },
+ [H616_RST_BUS_EMAC0] = { 0x097c, 16 },
+ [H616_RST_BUS_EMAC1] = { 0x097c, 17 },
+ [H616_RST_USB_PHY0] = { 0x0a70, 30 },
+ [H616_RST_USB_PHY1] = { 0x0a74, 30 },
+ [H616_RST_USB_PHY2] = { 0x0a78, 30 },
+ [H616_RST_USB_PHY3] = { 0x0a7c, 30 },
+ [H616_RST_BUS_OHCI0] = { 0x0a8c, 16 },
+ [H616_RST_BUS_OHCI1] = { 0x0a8c, 17 },
+ [H616_RST_BUS_OHCI2] = { 0x0a8c, 18 },
+ [H616_RST_BUS_OHCI3] = { 0x0a8c, 19 },
+ [H616_RST_BUS_EHCI0] = { 0x0a8c, 20 },
+ [H616_RST_BUS_EHCI1] = { 0x0a8c, 21 },
+ [H616_RST_BUS_EHCI2] = { 0x0a8c, 22 },
+ [H616_RST_BUS_EHCI3] = { 0x0a8c, 23 },
+};
+
+#define H616_R_RST_APB2_I2C 4
+#define H616_R_RST_APB2_RSB 7
+
+struct sxiccmu_ccu_bit sun50i_h616_r_resets[] = {
+ [H616_R_RST_APB2_I2C] = { 0x019c, 16 },
+ [H616_R_RST_APB2_RSB] = { 0x01bc, 16 },
};
/* R40 */
Index: sximmc.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sximmc.c,v
retrieving revision 1.12
diff -u -p -r1.12 sximmc.c
--- sximmc.c 24 Oct 2021 17:52:27 -0000 1.12
+++ sximmc.c 16 May 2023 12:37:57 -0000
@@ -205,6 +205,9 @@ struct sximmc_idma_descriptor {
#define SXIMMC_DMA_FTRGLEVEL_A20 0x20070008
#define SXIMMC_DMA_FTRGLEVEL_A80 0x200f0010
+#define SXIMMC_IDMA_ADDRSHIFT_NONE 0
+#define SXIMMC_IDMA_ADDRSHIFT_A100 2
+
int sximmc_match(struct device *, void *, void *);
void sximmc_attach(struct device *, struct device *, void *);
@@ -265,6 +268,7 @@ struct sximmc_softc {
uint32_t sc_intr_rint;
uint32_t sc_intr_mint;
uint32_t sc_idma_idst;
+ uint32_t sc_idma_addrshift;
uint32_t sc_gpio[4];
uint32_t sc_vmmc;
@@ -298,7 +302,9 @@ sximmc_match(struct device *parent, void
OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-mmc") ||
OF_is_compatible(faa->fa_node, "allwinner,sun9i-a80-mmc") ||
OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-mmc") ||
- OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc"));
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-mmc") ||
+ OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-emmc"));
}
int
@@ -394,6 +400,11 @@ sximmc_attach(struct device *parent, str
else
sc->sc_dma_ftrglevel = SXIMMC_DMA_FTRGLEVEL_A20;
+ if (OF_is_compatible(sc->sc_node, "allwinner,sun50i-a100-mmc"))
+ sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_A100;
+ else
+ sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_NONE;
+
if (sc->sc_use_dma) {
if (sximmc_idma_setup(sc) != 0) {
printf("%s: failed to setup DMA\n", self->dv_xname);
@@ -854,7 +865,7 @@ sximmc_dma_prepare(struct sximmc_softc *
bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr;
bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len;
dma[seg].dma_buf_size = htole32(len);
- dma[seg].dma_buf_addr = htole32(paddr);
+ dma[seg].dma_buf_addr = htole32(paddr >> sc->sc_idma_addrshift);
dma[seg].dma_config = htole32(SXIMMC_IDMA_CONFIG_CH |
SXIMMC_IDMA_CONFIG_OWN);
if (seg == 0) {
@@ -871,8 +882,9 @@ sximmc_dma_prepare(struct sximmc_softc *
dma[seg].dma_config |=
htole32(SXIMMC_IDMA_CONFIG_DIC);
dma[seg].dma_next = htole32(
- desc_paddr + ((seg + 1) *
- sizeof(struct sximmc_idma_descriptor)));
+ (desc_paddr + ((seg + 1) *
+ sizeof(struct sximmc_idma_descriptor))) >>
+ sc->sc_idma_addrshift);
}
}
@@ -897,7 +909,7 @@ sximmc_dma_prepare(struct sximmc_softc *
else
val |= SXIMMC_IDST_TRANSMIT_INT;
MMC_WRITE(sc, SXIMMC_IDIE, val);
- MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr);
+ MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr >> sc->sc_idma_addrshift);
MMC_WRITE(sc, SXIMMC_FTRGLEVEL, sc->sc_dma_ftrglevel);
return 0;
Index: sxipio.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio.c,v
retrieving revision 1.15
diff -u -p -r1.15 sxipio.c
--- sxipio.c 28 Jun 2022 23:43:12 -0000 1.15
+++ sxipio.c 16 May 2023 12:37:57 -0000
@@ -198,6 +198,14 @@ const struct sxipio_pins sxipio_pins[] =
"allwinner,sun50i-h6-r-pinctrl",
sun50i_h6_r_pins, nitems(sun50i_h6_r_pins)
},
+ {
+ "allwinner,sun50i-h616-pinctrl",
+ sun50i_h616_pins, nitems(sun50i_h616_pins)
+ },
+ {
+ "allwinner,sun50i-h616-r-pinctrl",
+ sun50i_h616_r_pins, nitems(sun50i_h616_r_pins)
+ },
};
int
Index: sxipio_pins.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio_pins.h,v
retrieving revision 1.8
diff -u -p -r1.8 sxipio_pins.h
--- sxipio_pins.h 28 Jun 2022 23:43:12 -0000 1.8
+++ sxipio_pins.h 16 May 2023 12:37:57 -0000
@@ -9858,3 +9858,600 @@ const struct sxipio_pin sun50i_h6_r_pins
{ "irq", 6 },
} },
};
+
+struct sxipio_pin sun50i_h616_pins[] = {
+ { SXIPIO_PIN(A, 0), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 1), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 2), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 3), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 4), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 5), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 6), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 7), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 8), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 9), {
+ { "emac1", 2 },
+ } },
+ { SXIPIO_PIN(A, 10), {
+ { "i2c3", 2 },
+ } },
+ { SXIPIO_PIN(A, 11), {
+ { "i2c3", 2 },
+ } },
+ { SXIPIO_PIN(A, 12), {
+ { "pwm5", 2 },
+ } },
+ { SXIPIO_PIN(C, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(C, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ { "spi0", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(F, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "clock", 3 },
+ { "jtag", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "clock", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s2", 2 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 17), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 18), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(G, 19), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm1", 4 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart0", 2 },
+ { "pwm3", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart0", 2 },
+ { "pwm4", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart5", 2 },
+ { "spdif", 3 },
+ { "pwm2", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart5", 2 },
+ { "pwm1", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spdif", 3 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3", 3 },
+ { "spi1", 4 },
+ { "i2c4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "i2s3_dout0", 3 },
+ { "spi1", 4 },
+ { "i2s3_din1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s3_din0", 3 },
+ { "spi1", 4 },
+ { "i2s3_dout1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(H, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "ir_rx", 3 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0", 4 },
+ { "hdmi", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0_dout0", 4 },
+ { "i2s0_din1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "dmic", 3 },
+ { "i2s0_din0", 4 },
+ { "i2s0_dout1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c0", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c0", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart2", 3 },
+ { "ts0", 4 },
+ { "i2c1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "i2c2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "pwm1", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart3", 3 },
+ { "ts0", 4 },
+ { "pwm2", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "pwm3", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "pwm4", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "clock", 5 },
+ { "irq", 6 },
+ } },
+ { SXIPIO_PIN(I, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "emac0", 2 },
+ { "uart4", 3 },
+ { "ts0", 4 },
+ { "clock", 5 },
+ { "irq", 6 },
+ } },
+};
+
+struct sxipio_pin sun50i_h616_r_pins[] = {
+ { SXIPIO_PIN(L, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_rsb", 2 },
+ { "s_i2c", 3 },
+ } },
+ { SXIPIO_PIN(L, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_rsb", 2 },
+ { "s_i2c", 3 },
+ } },
+};
Index: sxisyscon.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxisyscon.c,v
retrieving revision 1.2
diff -u -p -r1.2 sxisyscon.c
--- sxisyscon.c 24 Oct 2021 17:52:27 -0000 1.2
+++ sxisyscon.c 16 May 2023 12:37:57 -0000
@@ -52,7 +52,8 @@ sxisyscon_match(struct device *parent, v
if (OF_is_compatible(node, "allwinner,sun8i-h3-system-control") ||
OF_is_compatible(node, "allwinner,sun50i-a64-system-control") ||
OF_is_compatible(node, "allwinner,sun50i-h5-system-control") ||
- OF_is_compatible(node, "allwinner,sun50i-h6-system-control"))
+ OF_is_compatible(node, "allwinner,sun50i-h6-system-control") ||
+ OF_is_compatible(node, "allwinner,sun50i-h616-system-control"))
return 10; /* Must beat syscon(4). */
return 0;
--
SASANO Takayoshi (JG1UAA) <[email protected]>
