*Position: Physical Design Engineer* *Client : Mindtree*
*Location : Santa Clara & Chandler* *Requirements :* * Must have:* · 8/10+ years of hands-on experience in Physical Design, APR and Physical verification. · Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm and below ) · Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout · Experience in Synopsys ICC compiler, Cadence SOC encounter physical design tools. · Skill and experience in scripting using Tcl or Perl is highly desirable *TOTAL EXPERIENCE :* *RELEVANT EXPERIENCE :* *OFFICIAL NOTICE PERIOD :* *CURRENT RATE PER HOUR :* *VISA STATUS :* *EMAIL ID :-* *[email protected] <[email protected]>* -- You received this message because you are subscribed to the Google Groups "Android Developers" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/android-developers. To view this discussion on the web visit https://groups.google.com/d/msgid/android-developers/4d75e6c4-a7f5-452b-985d-d4b3eefa1d5c%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
