*RTL Design Engineer* (Modem design)
Location : Santa Clara Joining time : immediate Rate : Open for Full time or contract The Broad JD for the requirements is, · Verilog/VHDL RTL/Conformal Verification( LEC) · Working knowledge of Integrating multiple IPs and associated glue logic · Understanding of Power Management ( voltage domain, power domains, clock domains ) -- You received this message because you are subscribed to the Google Groups "Android Developers" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/android-developers. To view this discussion on the web visit https://groups.google.com/d/msgid/android-developers/8c60c5b7-1d63-45fc-9f6a-8bb9ba15e274%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
