From: Aurabindo Pillai <[email protected]> [Why&How] Export a debugfs file to report whether MALL cache is supported by the asic or not.
Reviewed-by: Hersen Wu <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7c21e21bcc51..b5f3b33b625d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3605,6 +3605,23 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); +/* + * Returns 1 if hardware supports MALL cache + * 0 otherwise. + */ +static int capabilities_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct dc_caps caps = adev->dm.dc->caps; + bool mall_supported = caps.mall_size_total; + + seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no"); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(capabilities); + /* * Temporary w/a to force sst sequence in M42D DP2 mst receiver * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst @@ -3798,6 +3815,8 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_mst_topology", 0444, root, adev, &mst_topo_fops); + debugfs_create_file("amdgpu_dm_capabilities", 0444, root, + adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, -- 2.37.3
