On 8/9/2023 11:16 AM, Srinivasan Shanmugam wrote:
This patch adds the missing code comment for memory barrier
WARNING: memory barrier without comment
+ mb();
WARNING: memory barrier without comment
+ mb();
Cc: Guchun Chen <[email protected]>
Cc: Christian König <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Pan, Xinhui" <[email protected]>
Signed-off-by: Srinivasan Shanmugam <[email protected]>
---
v3:
Corrected title message
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4f818f13dc9d..bb65e12ed027 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -305,10 +305,17 @@ size_t amdgpu_device_aper_access(struct amdgpu_device
*adev, loff_t pos,
if (write) {
memcpy_toio(addr, buf, count);
+ /* Make sure contents of system memory are
copied/flushed
+ * without messing up order of writes to PCI device I/O
memory
+ */
Make sure HDP write cache flush happens after the memory contents are
sent over PCIe.
mb();
amdgpu_device_flush_hdp(adev, NULL);
} else {
amdgpu_device_invalidate_hdp(adev, NULL);
+ /* Make sure contents of system memory
drained/invalidated
Similarly, make sure HDP read cache is invalidated before issuing a read
to the device. No reordering in both cases.
Thanks,
Lijo
+ * before copying contents from PCI device I/O memory
+ * to system memory
+ */
mb();
memcpy_fromio(buf, addr, count);
}
