Acked-by: Alex Deucher <[email protected]>
On Thu, May 11, 2023 at 9:20 PM Zhang, Jesse(Jie) <[email protected]> wrote: > > [AMD Official Use Only - General] > > > drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to > revision id. > > > > Due to the raven2 and raven/picasso maybe have the same GC_HWIP version. > > So differentiate them by revision id. > > > > Signed-off-by: shanshengwang <[email protected]> > > Signed-off-by: Jesse Zhang <[email protected]> > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > index e093e83ae739..1f4edfb96636 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > @@ -4000,30 +4000,27 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct > amdgpu_device *adev) > > clock = clock_lo | (clock_hi << 32ULL); > > break; > > case IP_VERSION(9, 1, 0): > > + case IP_VERSION(9, 2, 2): > > preempt_disable(); > > - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven); > > - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven); > > - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven); > > - /* The PWR TSC clock frequency is 100MHz, which sets 32-bit > carry over > > - * roughly every 42 seconds. > > - */ > > - if (hi_check != clock_hi) { > > + if (adev->rev_id >= 0x8) > > + { > > + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven2); > > + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven2); > > + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven2); > > + }else{ > > + clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven); > > clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven); > > - clock_hi = hi_check; > > + hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven); > > } > > - preempt_enable(); > > - clock = clock_lo | (clock_hi << 32ULL); > > - break; > > - case IP_VERSION(9, 2, 2): > > - preempt_disable(); > > - clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven2); > > - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven2); > > - hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_UPPER_Raven2); > > /* The PWR TSC clock frequency is 100MHz, which sets 32-bit > carry over > > - * roughly every 42 seconds. > > - */ > > + * roughly every 42 seconds. > > + */ > > if (hi_check != clock_hi) { > > - clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven2); > > + if (adev->rev_id >= 0x8) { > > + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven2); > > + }else{ > > + clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, > mmGOLDEN_TSC_COUNT_LOWER_Raven); > > + } > > clock_hi = hi_check; > > } > > preempt_enable(); > >
