This patch is, Reviewed-by: Luben Tuikov <[email protected]>
Regards, Luben On 2023-03-31 15:54, Alex Deucher wrote: > All chips that support RAS also support IP discovery, so > use the IP versions rather than a mix of IP versions and > asic types. Checking the validity of the atom_ctx pointer > is not required as the vbios is already fetched at this > point. > > v2: add comments to id asic types based on feedback from Luben > > Signed-off-by: Alex Deucher <[email protected]> > Cc: Luben Tuikov <[email protected]> > --- > .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 72 ++++++------------- > 1 file changed, 20 insertions(+), 52 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > index 3106fa8a15ef..c2c2a7718613 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c > @@ -106,48 +106,13 @@ > #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, > eeprom_control))->adev > > static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) > -{ > - if (adev->asic_type == CHIP_IP_DISCOVERY) { > - switch (adev->ip_versions[MP1_HWIP][0]) { > - case IP_VERSION(13, 0, 0): > - case IP_VERSION(13, 0, 10): > - return true; > - default: > - return false; > - } > - } > - > - return adev->asic_type == CHIP_VEGA20 || > - adev->asic_type == CHIP_ARCTURUS || > - adev->asic_type == CHIP_SIENNA_CICHLID || > - adev->asic_type == CHIP_ALDEBARAN; > -} > - > -static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev, > - struct amdgpu_ras_eeprom_control > *control) > -{ > - struct atom_context *atom_ctx = adev->mode_info.atom_context; > - > - if (!control || !atom_ctx) > - return false; > - > - if (strnstr(atom_ctx->vbios_version, > - "D342", > - sizeof(atom_ctx->vbios_version))) > - control->i2c_address = EEPROM_I2C_MADDR_0; > - else > - control->i2c_address = EEPROM_I2C_MADDR_4; > - > - return true; > -} > - > -static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev, > - struct amdgpu_ras_eeprom_control > *control) > { > switch (adev->ip_versions[MP1_HWIP][0]) { > + case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ > + case IP_VERSION(11, 0, 7): /* Sienna cichlid */ > case IP_VERSION(13, 0, 0): > + case IP_VERSION(13, 0, 2): /* Aldebaran */ > case IP_VERSION(13, 0, 10): > - control->i2c_address = EEPROM_I2C_MADDR_4; > return true; > default: > return false; > @@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device > *adev, > return true; > } > > - switch (adev->asic_type) { > - case CHIP_VEGA20: > - control->i2c_address = EEPROM_I2C_MADDR_0; > + switch (adev->ip_versions[MP1_HWIP][0]) { > + case IP_VERSION(11, 0, 2): > + /* VEGA20 and ARCTURUS */ > + if (adev->asic_type == CHIP_VEGA20) > + control->i2c_address = EEPROM_I2C_MADDR_0; > + else if (strnstr(atom_ctx->vbios_version, > + "D342", > + sizeof(atom_ctx->vbios_version))) > + control->i2c_address = EEPROM_I2C_MADDR_0; > + else > + control->i2c_address = EEPROM_I2C_MADDR_4; > return true; > - > - case CHIP_ARCTURUS: > - return __get_eeprom_i2c_addr_arct(adev, control); > - > - case CHIP_SIENNA_CICHLID: > + case IP_VERSION(11, 0, 7): > control->i2c_address = EEPROM_I2C_MADDR_0; > return true; > - > - case CHIP_ALDEBARAN: > + case IP_VERSION(13, 0, 2): > if (strnstr(atom_ctx->vbios_version, "D673", > sizeof(atom_ctx->vbios_version))) > control->i2c_address = EEPROM_I2C_MADDR_4; > else > control->i2c_address = EEPROM_I2C_MADDR_0; > return true; > - > - case CHIP_IP_DISCOVERY: > - return __get_eeprom_i2c_addr_ip_discovery(adev, control); > - > + case IP_VERSION(13, 0, 0): > + case IP_VERSION(13, 0, 10): > + control->i2c_address = EEPROM_I2C_MADDR_4; > + return true; > default: > return false; > }
