From: Lijo Lazar <[email protected]> The packet expects only 16 bits register offset. Hence pass register offset which is local to each XCC.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 451a7e58375e..2766e6ab5b1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -237,13 +237,14 @@ static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) { + uint32_t scratch_reg0_offset, xcc_offset; struct amdgpu_device *adev = ring->adev; uint32_t tmp = 0; unsigned i; int r; - /* scratch_reg0_offset is 32bit even with full XCD config */ - uint32_t scratch_reg0_offset; + /* Use register offset which is local to XCC in the packet */ + xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); WREG32(scratch_reg0_offset, 0xCAFEDEAD); @@ -252,7 +253,7 @@ static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) return r; amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); - amdgpu_ring_write(ring, scratch_reg0_offset - PACKET3_SET_UCONFIG_REG_START); + amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); amdgpu_ring_write(ring, 0xDEADBEEF); amdgpu_ring_commit(ring); -- 2.39.2
