From: Le Ma <[email protected]> Otherwise the EOP interrupt on non-AID0 cannot route to IH0.
Signed-off-by: Le Ma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 3811a7d82af9..bd375e472823 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -189,7 +189,10 @@ static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) { + int i; + for (i = 2; i < adev->gfx.num_xcd; i++) + WREG32_SOC15(GC, i, regGRBM_MCM_ADDR, 0x4); } static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, -- 2.39.2
