[Public] Hi Mario,
Thanks for your comments, it was on " origin/amd-staging-drm-next" Best Regards, Srini -----Original Message----- From: Limonciello, Mario <[email protected]> Sent: Thursday, March 23, 2023 6:03 PM To: SHANMUGAM, SRINIVASAN <[email protected]>; Koenig, Christian <[email protected]>; Deucher, Alexander <[email protected]>; Li, Candice <[email protected]>; Zhang, Hawking <[email protected]> Cc: [email protected] Subject: RE: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling [Public] > -----Original Message----- > From: SHANMUGAM, SRINIVASAN > <[email protected]> > Sent: Thursday, March 23, 2023 07:32 > To: Koenig, Christian <[email protected]>; Deucher, Alexander > <[email protected]>; Limonciello, Mario > <[email protected]>; Li, Candice <[email protected]>; Zhang, > Hawking <[email protected]> > Cc: [email protected]; SHANMUGAM, SRINIVASAN > <[email protected]> > Subject: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling > > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or > with non-zero value always evaluates to true > [-Werror,-Wtautological-bitwise- compare] > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. > > Cc: Christian König <[email protected]> > Cc: Alex Deucher <[email protected]> > Cc: Mario Limonciello <[email protected]> > Cc: Hawking Zhang <[email protected]> > Cc: Candice Li <[email protected]> > Signed-off-by: Srinivasan Shanmugam <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, > * nbio v4_3 only support fatal error interrupt > * to inform software that DF is freezed due to > -- > 2.25.1 This change generally makes sense for what you showed above, but what tree is this against? That doesn't look like amd-staging-drm-next, Linus' tree or even some recent tags.
