On Thu, Mar 9, 2023 at 10:24 AM Tom St Denis <[email protected]> wrote: > > Checked against database, copied from GC 9.4.2 header. > > Signed-off-by: Tom St Denis <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > .../include/asic_reg/gc/gc_10_1_0_offset.h | 4 ++ > .../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 54 +++++++++++++++++++ > .../include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++ > .../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 54 +++++++++++++++++++ > 4 files changed, 116 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > index 18d34bbceebe..79c41004c0b6 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h > @@ -4868,6 +4868,10 @@ > #define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX > 0 > #define mmCP_ME2_PIPE3_INT_STATUS > 0x1e34 > #define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX > 0 > +#define mmCP_ME1_INT_STAT_DEBUG > 0x1e35 > +#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX > 0 > +#define mmCP_ME2_INT_STAT_DEBUG > 0x1e36 > +#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX > 0 > #define mmCP_GFX_QUEUE_INDEX > 0x1e37 > #define mmCP_GFX_QUEUE_INDEX_BASE_IDX > 0 > #define mmCC_GC_EDC_CONFIG > 0x1e38 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > index 4127896ffcdf..52043e143067 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h > @@ -18680,6 +18680,60 @@ > //CC_GC_EDC_CONFIG > #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT > 0x1 > #define CC_GC_EDC_CONFIG__DIS_EDC_MASK > 0x00000002L > +//CP_ME1_INT_STAT_DEBUG > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > +//CP_ME2_INT_STAT_DEBUG > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > //CP_ME1_PIPE_PRIORITY_CNTS > #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT > 0x0 > #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT > 0x8 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > index 3973110f149c..a734abaa91a5 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > @@ -4531,6 +4531,10 @@ > #define mmCP_GFX_QUEUE_INDEX_BASE_IDX > 0 > #define mmCC_GC_EDC_CONFIG > 0x1e38 > #define mmCC_GC_EDC_CONFIG_BASE_IDX > 0 > +#define mmCP_ME1_INT_STAT_DEBUG > 0x1e35 > +#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX > 0 > +#define mmCP_ME2_INT_STAT_DEBUG > 0x1e36 > +#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX > 0 > #define mmCP_ME1_PIPE_PRIORITY_CNTS > 0x1e39 > #define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX > 0 > #define mmCP_ME1_PIPE0_PRIORITY > 0x1e3a > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > index d4e8ff22ecb8..d7a17bae2584 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > @@ -17028,6 +17028,60 @@ > //CC_GC_EDC_CONFIG > #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT > 0x1 > #define CC_GC_EDC_CONFIG__DIS_EDC_MASK > 0x00000002L > +//CP_ME1_INT_STAT_DEBUG > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > +//CP_ME2_INT_STAT_DEBUG > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > //CP_ME1_PIPE_PRIORITY_CNTS > #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT > 0x0 > #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT > 0x8 > -- > 2.37.2 >
