[AMD Official Use Only - General] Ping...
> -----Original Message----- > From: Zhou1, Tao <[email protected]> > Sent: Wednesday, November 2, 2022 10:36 AM > To: [email protected]; Zhang, Hawking > <[email protected]>; Deucher, Alexander > <[email protected]> > Cc: Zhou1, Tao <[email protected]>; Lazar, Lijo <[email protected]> > Subject: [PATCH 2/2] drm/amdgpu: enable RAS poison for VCN 2.6 > > Configure related settings to enable it. > > Signed-off-by: Tao Zhou <[email protected]> > Signed-off-by: Lijo Lazar <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 29 > +++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > index 8a7006d62a87..43eefed30057 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > @@ -770,6 +770,33 @@ static void vcn_v2_5_enable_clock_gating(struct > amdgpu_device *adev) > } > } > > +static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, > + bool indirect) > +{ > + uint32_t tmp; > + > + if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0)) > + return; > + > + tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | > + VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | > + VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | > + VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; > + WREG32_SOC15_DPG_MODE(inst_idx, > + SOC15_DPG_MODE_OFFSET(VCN, 0, > regVCN_RAS_CNTL), > + tmp, 0, indirect); > + > + tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; > + WREG32_SOC15_DPG_MODE(inst_idx, > + SOC15_DPG_MODE_OFFSET(VCN, 0, > regUVD_VCPU_INT_EN), > + tmp, 0, indirect); > + > + tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; > + WREG32_SOC15_DPG_MODE(inst_idx, > + SOC15_DPG_MODE_OFFSET(VCN, 0, > regUVD_SYS_INT_EN), > + tmp, 0, indirect); > +} > + > static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, > bool indirect) { > volatile struct amdgpu_fw_shared *fw_shared = adev- > >vcn.inst[inst_idx].fw_shared.cpu_addr; > @@ -849,6 +876,8 @@ static int vcn_v2_5_start_dpg_mode(struct > amdgpu_device *adev, int inst_idx, boo > WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( > VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); > > + vcn_v2_6_enable_ras(adev, inst_idx, indirect); > + > /* unblock VCPU register access */ > WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( > VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); > -- > 2.35.1
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