[PATCH 08/19] drm/amdgpu: add gfx support for GC 11.0.4

[Yifan Zhang]

this patch to add GC 11.0.4 gfx support to gfx11 implementation.

Signed-off-by: Yifan Zhang <yifan1.zh...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 9d2c6523f546..bf78440e1e70 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -77,6 +77,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
 
 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
 {
@@ -262,6 +266,7 @@ static void gfx_v11_0_init_golden_registers(struct 
amdgpu_device *adev)
 {
        switch (adev->ip_versions[GC_HWIP][0]) {
        case IP_VERSION(11, 0, 1):
+       case IP_VERSION(11, 0, 4):
                soc15_program_register_sequence(adev,
                                                golden_settings_gc_11_0_1,
                                                (const 
u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
@@ -855,6 +860,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device 
*adev)
                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
                break;
        case IP_VERSION(11, 0, 1):
+       case IP_VERSION(11, 0, 4):
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1284,6 +1290,7 @@ static int gfx_v11_0_sw_init(void *handle)
        case IP_VERSION(11, 0, 1):
        case IP_VERSION(11, 0, 2):
        case IP_VERSION(11, 0, 3):
+       case IP_VERSION(11, 0, 4):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
@@ -2486,7 +2493,8 @@ static int 
gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
        for (i = 0; i < adev->usec_timeout; i++) {
                cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
 
-               if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
+               if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) ||
+                               adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 
0, 4))
                        bootload_status = RREG32_SOC15(GC, 0,
                                        regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
                else
-- 
2.37.3