[AMD Official Use Only] Hi Paul,
This is not related to any issue. Kind regards, Ruili -----Original Message----- From: Paul Menzel <[email protected]> Sent: 2022年3月29日 16:16 To: Ji, Ruili <[email protected]> Cc: [email protected]; Zhang, Yifan <[email protected]>; Liu, Aaron <[email protected]>; Liang, Prike <[email protected]>; Huang, Ray <[email protected]>; Deucher, Alexander <[email protected]>; Ji, Ruili <[email protected]> Subject: Re: [PATCH V2] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address [CAUTION: External Email] Dear Ruili, Thank you for your patch. Am 28.03.22 um 06:58 schrieb Ji, Ruili: > From: Ruili Ji <[email protected]> > > gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for > GCR_GENERAL_CNTL Is any “user-visible“ problem fixed by this? Please add a Fixes tag. Kind regards, Paul > Signed-off-by: Ruili Ji <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 99df18ae7316..e4c9d92ac381 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_3[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, > 0x00000500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1ffff, 0x00000500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, > 0x32103210), @@ -3436,7 +3436,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_6[] = > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, > 0x00000500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1ffff, 0x00000500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, > 0x32103210), @@ -3461,7 +3461,7 @@ static const struct soc15_reg_golden > golden_settings_gc_10_3_7[] = { > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, > 0x00000500), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, > + 0x1ff1ffff, 0x00000500), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, > 0x32103210), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, > 0x32103210),
