From: Qingqing Zhuo <[email protected]> DC core changes for DCN 3.1.5.
Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 ++++++++++--- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 48858e31b092..417976426bbf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3236,9 +3236,16 @@ bool dc_link_setup_psr(struct dc_link *link, /*skip power down the single pipe since it blocks the cstate*/ #if defined(CONFIG_DRM_AMD_DC_DCN) if (link->ctx->asic_id.chip_family >= FAMILY_RV) { - psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; - if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10) - psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false; + switch(link->ctx->asic_id.chip_family) { + case FAMILY_YELLOW_CARP: + case AMDGPU_FAMILY_GC_10_3_6: + if(!dc->debug.disable_z10) + psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false; + break; + default: + psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; + break; + } } #else if (link->ctx->asic_id.chip_family >= FAMILY_RV) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 004a299228ab..d266253a78a2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -66,6 +66,7 @@ #include "dcn302/dcn302_resource.h" #include "dcn303/dcn303_resource.h" #include "dcn31/dcn31_resource.h" +#include "dcn315/dcn315_resource.h" #include "dcn316/dcn316_resource.h" #endif @@ -156,6 +157,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_3_1; break; + case AMDGPU_FAMILY_GC_10_3_6: + if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_15; + break; case AMDGPU_FAMILY_GC_10_3_7: if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_3_16; @@ -251,6 +256,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_3_1: res_pool = dcn31_create_resource_pool(init_data, dc); break; + case DCN_VERSION_3_15: + res_pool = dcn315_create_resource_pool(init_data, dc); + break; case DCN_VERSION_3_16: res_pool = dcn316_create_resource_pool(init_data, dc); break; -- 2.35.1
