[Public] Series is: Reviewed-by: Guchun Chen [email protected]<mailto:[email protected]>
Regards, Guchun From: Deucher, Alexander <[email protected]> Sent: Saturday, January 22, 2022 1:00 AM To: Chen, Guchun <[email protected]>; [email protected] Subject: Re: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval [Public] It just changes the limit for when we use msleep vs udelay, not the units. Alex ________________________________ From: Chen, Guchun <[email protected]<mailto:[email protected]>> Sent: Thursday, January 20, 2022 8:49 PM To: Deucher, Alexander <[email protected]<mailto:[email protected]>>; [email protected]<mailto:[email protected]> <[email protected]<mailto:[email protected]>> Cc: Deucher, Alexander <[email protected]<mailto:[email protected]>> Subject: RE: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval [Public] If we change if condition, how about the division by "wait_in_micro_secs/1000", as the sleep time is less now. Shall we adjust it as well? Regards, Guchun -----Original Message----- From: amd-gfx <[email protected]<mailto:[email protected]>> On Behalf Of Alex Deucher Sent: Friday, January 21, 2022 2:04 AM To: [email protected]<mailto:[email protected]> Cc: Deucher, Alexander <[email protected]<mailto:[email protected]>> Subject: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval Some architectures (e.g., ARM) have relatively low udelay limits. On most architectures, anything longer than 2000us is not recommended. Change the check to align with other similar checks in DC. Signed-off-by: Alex Deucher <[email protected]<mailto:[email protected]>> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 1f8831156bc4..aa1c67c3c386 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -202,7 +202,7 @@ void dp_wait_for_training_aux_rd_interval( uint32_t wait_in_micro_secs) { #if defined(CONFIG_DRM_AMD_DC_DCN) - if (wait_in_micro_secs > 16000) + if (wait_in_micro_secs > 1000) msleep(wait_in_micro_secs/1000); else udelay(wait_in_micro_secs); -- 2.34.1
