Re: [PATCH 1/2] drm/amdgpu: enable Navi 48-bit IH timestamp counter

[Christian König]

Am 23.11.21 um 17:03 schrieb Philip Yang:

By default this timestamp is 32 bit counter. It gets overflowed in
around 10 minutes.

Signed-off-by: Philip Yang <philip.y...@amd.com>

Reviewed-by: Christian König <christian.koe...@amd.com> for the series.

---
  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 1d8414c3fadb..dafad6030947 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -160,6 +160,7 @@ static int navi10_ih_toggle_ring_interrupts(struct 
amdgpu_device *adev,

tmp = RREG32(ih_regs->ih_rb_cntl);

        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
+       tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
        /* enable_intr field is only valid in ring0 */
        if (ih == &adev->irq.ih)
                tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 
0));