Am 2021-04-21 um 10:24 p.m. schrieb Jonathan Kim: > In order to support multi-process debugging, HWS PM4 packet > MAP_PROCESS requires an extension of 5 DWORDS to support targeting of > per-vmid SPI debug control registers as well as watch points per process. > > v2: align upstream with internal new MEC FW > > Signed-off-by: Jonathan Kim <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]> > --- > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 9 +- > .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 +- > .../drm/amd/amdkfd/kfd_packet_manager_v9.c | 58 +++++++++++- > .../amd/amdkfd/kfd_pm4_headers_aldebaran.h | 93 +++++++++++++++++++ > drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + > 5 files changed, 161 insertions(+), 4 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > index b31bae91fbd0..348fd3e49017 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > @@ -26,6 +26,7 @@ > #include "kfd_priv.h" > #include "kfd_device_queue_manager.h" > #include "kfd_pm4_headers_vi.h" > +#include "kfd_pm4_headers_aldebaran.h" > #include "cwsr_trap_handler.h" > #include "kfd_iommu.h" > #include "amdgpu_amdkfd.h" > @@ -714,7 +715,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, > struct drm_device *ddev, > const struct kgd2kfd_shared_resources *gpu_resources) > { > - unsigned int size; > + unsigned int size, map_process_packet_size; > > kfd->ddev = ddev; > kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, > @@ -749,7 +750,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, > * calculate max size of runlist packet. > * There can be only 2 packets at once > */ > - size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + > + map_process_packet_size = > + kfd->device_info->asic_family == CHIP_ALDEBARAN ? > + sizeof(struct pm4_mes_map_process_aldebaran) : > + sizeof(struct pm4_mes_map_process); > + size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + > max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) > + sizeof(struct pm4_mes_runlist)) * 2; > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c > b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c > index e840dd581719..0ce507d7208a 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c > @@ -242,7 +242,6 @@ int pm_init(struct packet_manager *pm, struct > device_queue_manager *dqm) > case CHIP_RAVEN: > case CHIP_RENOIR: > case CHIP_ARCTURUS: > - case CHIP_ALDEBARAN: > case CHIP_NAVI10: > case CHIP_NAVI12: > case CHIP_NAVI14: > @@ -252,6 +251,9 @@ int pm_init(struct packet_manager *pm, struct > device_queue_manager *dqm) > case CHIP_DIMGREY_CAVEFISH: > pm->pmf = &kfd_v9_pm_funcs; > break; > + case CHIP_ALDEBARAN: > + pm->pmf = &kfd_aldebaran_pm_funcs; > + break; > default: > WARN(1, "Unexpected ASIC family %u", > dqm->dev->device_info->asic_family); > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c > b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c > index e3ba0cd3b6fa..7ea3f671b325 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c > @@ -24,6 +24,7 @@ > #include "kfd_kernel_queue.h" > #include "kfd_device_queue_manager.h" > #include "kfd_pm4_headers_ai.h" > +#include "kfd_pm4_headers_aldebaran.h" > #include "kfd_pm4_opcodes.h" > #include "gc/gc_10_1_0_sh_mask.h" > > @@ -35,7 +36,6 @@ static int pm_map_process_v9(struct packet_manager *pm, > > packet = (struct pm4_mes_map_process *)buffer; > memset(buffer, 0, sizeof(struct pm4_mes_map_process)); > - > packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, > sizeof(struct pm4_mes_map_process)); > packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; > @@ -73,6 +73,45 @@ static int pm_map_process_v9(struct packet_manager *pm, > return 0; > } > > +static int pm_map_process_aldebaran(struct packet_manager *pm, > + uint32_t *buffer, struct qcm_process_device *qpd) > +{ > + struct pm4_mes_map_process_aldebaran *packet; > + uint64_t vm_page_table_base_addr = qpd->page_table_base; > + > + packet = (struct pm4_mes_map_process_aldebaran *)buffer; > + memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran)); > + packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, > + sizeof(struct pm4_mes_map_process_aldebaran)); > + packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; > + packet->bitfields2.process_quantum = 10; > + packet->bitfields2.pasid = qpd->pqm->process->pasid; > + packet->bitfields14.gds_size = qpd->gds_size & 0x3F; > + packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF; > + packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : > 0; > + packet->bitfields14.num_oac = qpd->num_oac; > + packet->bitfields14.sdma_enable = 1; > + packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count; > + > + packet->sh_mem_config = qpd->sh_mem_config; > + packet->sh_mem_bases = qpd->sh_mem_bases; > + if (qpd->tba_addr) { > + packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); > + packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); > + packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); > + } > + > + packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); > + packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); > + > + packet->vm_context_page_table_base_addr_lo32 = > + lower_32_bits(vm_page_table_base_addr); > + packet->vm_context_page_table_base_addr_hi32 = > + upper_32_bits(vm_page_table_base_addr); > + > + return 0; > +} > + > static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer, > uint64_t ib, size_t ib_size_in_dwords, bool chain) > { > @@ -324,3 +363,20 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = { > .query_status_size = sizeof(struct pm4_mes_query_status), > .release_mem_size = 0, > }; > + > +const struct packet_manager_funcs kfd_aldebaran_pm_funcs = { > + .map_process = pm_map_process_aldebaran, > + .runlist = pm_runlist_v9, > + .set_resources = pm_set_resources_v9, > + .map_queues = pm_map_queues_v9, > + .unmap_queues = pm_unmap_queues_v9, > + .query_status = pm_query_status_v9, > + .release_mem = NULL, > + .map_process_size = sizeof(struct pm4_mes_map_process_aldebaran), > + .runlist_size = sizeof(struct pm4_mes_runlist), > + .set_resources_size = sizeof(struct pm4_mes_set_resources), > + .map_queues_size = sizeof(struct pm4_mes_map_queues), > + .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues), > + .query_status_size = sizeof(struct pm4_mes_query_status), > + .release_mem_size = 0, > +}; > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h > b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h > new file mode 100644 > index 000000000000..f795ec815e2a > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h > @@ -0,0 +1,93 @@ > +/* > + * Copyright 2020 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +/*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/ > + > +#ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED > +#define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED > + > +struct pm4_mes_map_process_aldebaran { > + union { > + union PM4_MES_TYPE_3_HEADER header; /* header */ > + uint32_t ordinal1; > + }; > + > + union { > + struct { > + uint32_t pasid:16; /* 0 - 15 */ > + uint32_t single_memops:1; /* 16 */ > + uint32_t reserved1:1; /* 17 */ > + uint32_t debug_vmid:4; /* 18 - 21 */ > + uint32_t new_debug:1; /* 22 */ > + uint32_t tmz:1; /* 23 */ > + uint32_t diq_enable:1; /* 24 */ > + uint32_t process_quantum:7; /* 25 - 31 */ > + } bitfields2; > + uint32_t ordinal2; > + }; > + > + uint32_t vm_context_page_table_base_addr_lo32; > + > + uint32_t vm_context_page_table_base_addr_hi32; > + > + uint32_t sh_mem_bases; > + > + uint32_t sh_mem_config; > + > + uint32_t sq_shader_tba_lo; > + > + uint32_t sq_shader_tba_hi; > + > + uint32_t sq_shader_tma_lo; > + > + uint32_t sq_shader_tma_hi; > + > + uint32_t reserved6; > + > + uint32_t gds_addr_lo; > + > + uint32_t gds_addr_hi; > + > + union { > + struct { > + uint32_t num_gws:7; > + uint32_t sdma_enable:1; > + uint32_t num_oac:4; > + uint32_t gds_size_hi:4; > + uint32_t gds_size:6; > + uint32_t num_queues:10; > + } bitfields14; > + uint32_t ordinal14; > + }; > + > + uint32_t spi_gdbg_per_vmid_cntl; > + > + uint32_t tcp_watch_cntl[4]; > + > + uint32_t completion_signal_lo; > + > + uint32_t completion_signal_hi; > + > +}; > + > +#endif > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > index a1ddcf6446db..64552f6b8ba4 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > @@ -1088,6 +1088,7 @@ struct packet_manager_funcs { > > extern const struct packet_manager_funcs kfd_vi_pm_funcs; > extern const struct packet_manager_funcs kfd_v9_pm_funcs; > +extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; > > int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); > void pm_uninit(struct packet_manager *pm, bool hanging); _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
