From: Roman Li <[email protected]> Update dm for vangogh support.
Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e8177656e083..3cf4e08931bb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -100,6 +100,10 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); +#endif #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); @@ -1135,6 +1139,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_DC_DCN3_0) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case CHIP_VANGOGH: #endif return 0; case CHIP_NAVI12: @@ -1242,6 +1249,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; break; #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case CHIP_VANGOGH: + dmub_asic = DMUB_ASIC_DCN301; + fw_name_dmub = FIRMWARE_VANGOGH_DMUB; + break; +#endif default: /* ASIC doesn't support DMUB. */ @@ -3362,6 +3375,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) #if defined(CONFIG_DRM_AMD_DC_DCN3_0) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case CHIP_VANGOGH: #endif if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); @@ -3609,6 +3625,13 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + case CHIP_VANGOGH: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; + break; +#endif case CHIP_NAVI14: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; @@ -3928,6 +3951,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, #if defined(CONFIG_DRM_AMD_DC_DCN3_0) adev->asic_type == CHIP_SIENNA_CICHLID || adev->asic_type == CHIP_NAVY_FLOUNDER || +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + adev->asic_type == CHIP_VANGOGH || #endif adev->asic_type == CHIP_RENOIR || adev->asic_type == CHIP_RAVEN) { -- 2.25.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
