[AMD Public Use]
- if (adev->asic_type != CHIP_VEGA20 && adev->asic_type !=
CHIP_ARCTURUS)
+ if (adev->asic_type != CHIP_VEGA20 &&
+ adev->asic_type != CHIP_ARCTURUS &&
+ adev->asic_type != CHIP_SIENNA_CICHLID)
return 0;
Does it make sense to check UMC RAS availability through
amdgpu_ras_is_supported, instead of check specific ASIC type one by one?
Also, it would be good to merge the upcoming logic from Guchun where we have a
gloal flag to mark the availability of bad page retirement.
Thoughts?
Regards,
Hawking
From: Clements, John <[email protected]>
Sent: Tuesday, July 21, 2020 18:02
To: amd-gfx list <[email protected]>; Zhang, Hawking
<[email protected]>
Subject: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid
[AMD Public Use]
Submitting patch to enable RAS EEPROM support for sienna chichlid
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