It was merged into amd-staging-drm-next. I'm not absolutely sure, but I think we need to invalidate before IBs if an IB is cached in L2 and the CPU has updated it. It can only be cached in L2 if something other than CP has read it or written to it without invalidation. CP reads don't cache it but they can hit the cache if it's already cached.
For CE, we need to invalidate before the IB in the kernel, because CE IBs can't do cache invalidations IIRC. This is the number one reason for merging the already pushed commits. Marek On Sat., Apr. 25, 2020, 11:03 Christian König, < [email protected]> wrote: > Was that patch set actually merged upstream? My last status is that we > couldn't find a reason why we need to do this in the kernel. > > Christian. > > Am 25.04.20 um 10:52 schrieb Marek Olšák: > > This was missed. > > Marek > > _______________________________________________ > amd-gfx mailing > [email protected]https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > >
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