[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Emily Deng <[email protected]>
Best wishes Emily Deng >-----Original Message----- >From: amd-gfx <[email protected]> On Behalf Of >Frank.Min >Sent: Thursday, December 19, 2019 7:44 PM >To: [email protected] >Cc: Min, Frank <[email protected]> >Subject: [PATCH 1/2] drm/amdgpu: remove FB location config for sriov > >FB location is already programmed by HV driver for arcutus so remove this part > >Change-Id: Ia357ae716bfc3084a4dd277ade219e57092f9b42 >Signed-off-by: Frank.Min <[email protected]> >--- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +- >drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 16 ---------------- > 2 files changed, 1 insertion(+), 17 deletions(-) > >diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >index e91bd7945777..e9a9d24c2b7f 100644 >--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >@@ -264,7 +264,7 @@ static void gfxhub_v1_0_program_invalidation(struct >amdgpu_device *adev) > > int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) { >- if (amdgpu_sriov_vf(adev)) { >+ if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { > /* > * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase >they are > * VF copy registers so vbios post doesn't program them, for > diff >--git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c >b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c >index d9301e80522a..ac61206c4ce6 100644 >--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c >+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c >@@ -368,22 +368,6 @@ int mmhub_v9_4_gart_enable(struct amdgpu_device >*adev) > int i; > > for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { >- if (amdgpu_sriov_vf(adev)) { >- /* >- * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, >becuase >- * they are VF copy registers so vbios post doesn't >- * program them, for SRIOV driver need to program >them >- */ >- WREG32_SOC15_OFFSET(MMHUB, 0, >- >mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE, >- i * MMHUB_INSTANCE_REGISTER_OFFSET, >- adev->gmc.vram_start >> 24); >- WREG32_SOC15_OFFSET(MMHUB, 0, >- >mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP, >- i * MMHUB_INSTANCE_REGISTER_OFFSET, >- adev->gmc.vram_end >> 24); >- } >- > /* GART Enable. */ > mmhub_v9_4_init_gart_aperture_regs(adev, i); > mmhub_v9_4_init_system_aperture_regs(adev, i); >-- >2.17.1 > >_______________________________________________ >amd-gfx mailing list >[email protected] >https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.fre >edesktop.org%2Fmailman%2Flistinfo%2Famd- >gfx&data=02%7C01%7CEmily.Deng%40amd.com%7C564215fe64b245954 >97408d78478b687%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C >637123526651355885&sdata=Aeag0%2FF6lQHe70aot5ZzB5UP1rZxsEZO2 >WfLyJv1njg%3D&reserved=0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
