Add VML2 and ATCL2 ECC registers to support VEGA20 RAS
Change-Id: I8860f2e37fa7afd8d6123290fb7b9dcee56edd6e
Signed-off-by: Dennis Li <[email protected]>
---
.../amd/include/asic_reg/gc/gc_9_0_offset.h | 18 ++++++++++++++++--
.../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 18 ++++++++++++++++--
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index ca16d9125fbc..2bfaaa8157d0 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -1146,7 +1146,14 @@
#define mmATC_L2_MEM_POWER_LS_BASE_IDX
0
#define mmATC_L2_CGTT_CLK_CTRL
0x080c
#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX
0
-
+#define mmATC_L2_CACHE_4K_EDC_INDEX
0x080e
+#define mmATC_L2_CACHE_4K_EDC_INDEX_BASE_IDX
0
+#define mmATC_L2_CACHE_2M_EDC_INDEX
0x080f
+#define mmATC_L2_CACHE_2M_EDC_INDEX_BASE_IDX
0
+#define mmATC_L2_CACHE_4K_EDC_CNT
0x0810
+#define mmATC_L2_CACHE_4K_EDC_CNT_BASE_IDX
0
+#define mmATC_L2_CACHE_2M_EDC_CNT
0x0811
+#define mmATC_L2_CACHE_2M_EDC_CNT_BASE_IDX
0
// addressBlock: gc_utcl2_vml2pfdec
// base address: 0xa100
@@ -1206,7 +1213,14 @@
#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX
0
#define mmVM_L2_CGTT_CLK_CTRL
0x085e
#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX
0
-
+#define mmVM_L2_MEM_ECC_INDEX
0x0860
+#define mmVM_L2_MEM_ECC_INDEX_BASE_IDX
0
+#define mmVM_L2_WALKER_MEM_ECC_INDEX
0x0861
+#define mmVM_L2_WALKER_MEM_ECC_INDEX_BASE_IDX
0
+#define mmVM_L2_MEM_ECC_CNT
0x0862
+#define mmVM_L2_MEM_ECC_CNT_BASE_IDX
0
+#define mmVM_L2_WALKER_MEM_ECC_CNT
0x0863
+#define mmVM_L2_WALKER_MEM_ECC_CNT_BASE_IDX
0
// addressBlock: gc_utcl2_vml2vcdec
// base address: 0xa200
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
index 064c4bb1dc62..d4c613a85352 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
@@ -6661,7 +6661,6 @@
#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
0x00FF0000L
#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
0xFF000000L
-
// addressBlock: gc_utcl2_vml2pfdec
//VM_L2_CNTL
#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT
0x0
@@ -6991,7 +6990,22 @@
#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
0x00008000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
0x00FF0000L
#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
0xFF000000L
-
+//VM_L2_MEM_ECC_INDEX
+#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT
0x0
+#define VM_L2_MEM_ECC_INDEX__INDEX_MASK
0x000000FFL
+//VM_L2_WALKER_MEM_ECC_INDEX
+#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT
0x0
+#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK
0x000000FFL
+//VM_L2_MEM_ECC_CNT
+#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT
0xc
+#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT
0xe
+#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK
0x00003000L
+#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK
0x0000C000L
+//VM_L2_WALKER_MEM_ECC_CNT
+#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT
0xc
+#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT
0xe
+#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK
0x00003000L
+#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK
0x0000C000L
// addressBlock: gc_utcl2_vml2vcdec
//VM_CONTEXT0_CNTL
--
2.17.1
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