That was my thought too. I'll do that as a future patch. Kent
From: Kuehling, Felix <[email protected]> Sent: Tuesday, July 23, 2019 2:51 PM To: Russell, Kent <[email protected]>; Deucher, Alexander <[email protected]>; [email protected] Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM This was needed for VI chips before Fiji. I think that means Tonga, Topaz and Carrizo. As the list of supported ASICs keeps growing, we should change the condition to list only the chips that need the workaround, instead of adding every future chip to the list that don't. Regards, Felix -- F e l i x K u e h l i n g PMTS Software Development Engineer | Linux Compute Kernel 1 Commerce Valley Dr. East, Markham, ON L3T 7X6 Canada (O) +1(289)695-1597 _ _ _ _____ _____ / \ | \ / | | _ \ \ _ | / A \ | \M/ | | |D) ) /|_| | /_/ \_\ |_| |_| |_____/ |__/ \| facebook.com/AMD | amd.com ________________________________ From: amd-gfx <[email protected]<mailto:[email protected]>> on behalf of Russell, Kent <[email protected]<mailto:[email protected]>> Sent: Tuesday, July 23, 2019 11:18:52 AM To: Deucher, Alexander <[email protected]<mailto:[email protected]>>; [email protected]<mailto:[email protected]> <[email protected]<mailto:[email protected]>> Subject: RE: [PATCH] drm/amdkfd: Fix byte align on VegaM I'll push this, I was just wondering if Felix could confirm if the TLB workaround was only for Tonga/Topaz, in which case we could check for that instead of having to expand the list in situations like this, to say "if FAMILY_VI && (TOPAZ || TONGA) then". That way it's explicitly applying the workaround to the affected ASICs instead of implicitly not-applying the workaround to unaffected ASICs. Kent From: Deucher, Alexander <[email protected]<mailto:[email protected]>> Sent: Tuesday, July 23, 2019 11:16 AM To: Russell, Kent <[email protected]<mailto:[email protected]>>; [email protected]<mailto:[email protected]> Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM Reviewed-by: Alex Deucher <[email protected]<mailto:[email protected]>> ________________________________ From: amd-gfx <[email protected]<mailto:[email protected]>> on behalf of Russell, Kent <[email protected]<mailto:[email protected]>> Sent: Tuesday, July 23, 2019 10:22 AM To: [email protected]<mailto:[email protected]> <[email protected]<mailto:[email protected]>> Cc: Russell, Kent <[email protected]<mailto:[email protected]>> Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM This was missed during the addition of VegaM support Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670 Signed-off-by: Kent Russell <[email protected]<mailto:[email protected]>> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f5ecf28eb37c..3179117ac434 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( adev->asic_type != CHIP_FIJI && adev->asic_type != CHIP_POLARIS10 && adev->asic_type != CHIP_POLARIS11 && - adev->asic_type != CHIP_POLARIS12) ? + adev->asic_type != CHIP_POLARIS12 && + adev->asic_type != CHIP_VEGAM) ? VI_BO_SIZE_ALIGN : 1; mapping_flags = AMDGPU_VM_PAGE_READABLE; -- 2.17.1 _______________________________________________ amd-gfx mailing list [email protected]<mailto:[email protected]> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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