> -----Original Message-----
> From: amd-gfx <[email protected]> On Behalf Of
> Christian König
> Sent: Tuesday, May 14, 2019 6:34 AM
> To: Zhou, Tiecheng <[email protected]>; amd-
> [email protected]
> Cc: Deng, Emily <[email protected]>
> Subject: Re: [PATCH] drm/amdgpu/sriov: Need to initialize the
> HDP_NONSURFACE_BAStE
>
> [CAUTION: External Email]
>
> Am 14.05.19 um 12:24 schrieb Tiecheng Zhou:
> > it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using
> > the value left by a previous VM under sriov scenario.
> >
> > Signed-off-by: Emily Deng <[email protected]>
> > Signed-off-by: Tiecheng Zhou <[email protected]>
>
> Would it hurt us to also do this on bare metal?
>
Vbios Asic_init handles this for us on bare metal.
Alex
> Apart from that looks good to me,
> Christian.
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index be729e7..e96684e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -1181,6 +1181,11 @@ static int gmc_v9_0_gart_enable(struct
> amdgpu_device *adev)
> > tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
> > WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
> >
> > + if (amdgpu_sriov_vf(adev)) {
> > + WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev-
> >gmc.vram_start >> 8));
> > + WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev-
> >gmc.vram_start >> 40));
> > + }
> > +
> > /* After HDP is initialized, flush HDP.*/
> > adev->nbio_funcs->hdp_flush(adev, NULL);
> >
>
> _______________________________________________
> amd-gfx mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
