We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. In this patch ,disabling low memory P state only when video size >= 4k. Multiple runs of power measurement shows no imapct
Signed-off-by: suresh guttula <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 17 +++++++++++++++++ drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 4 +++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index e5a6db6..6902719 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -38,6 +38,7 @@ #include "amdgpu_uvd.h" #include "cikd.h" #include "uvd/uvd_4_2_d.h" +#include "hwmgr.h" /* 1 second timeout */ #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -78,6 +79,7 @@ #define UVD_GPCOM_VCPU_DATA1 0x03c5 #define UVD_NO_OP 0x03ff #define UVD_BASE_SI 0x3800 +#define WIDTH_4K 3840 /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -528,6 +530,21 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; unsigned min_ctx_size = ~0; + //disable Low Memory PState for UVD(4k videos) + if (adev->asic_type == CHIP_STONEY && width >= WIDTH_4K) { + struct pp_hwmgr *hwmgr; + struct pp_instance *pp_handle = + (struct pp_instance *)adev->powerplay.pp_handle; + if (pp_handle) { + hwmgr = pp_handle->hwmgr; + if (hwmgr && hwmgr->hwmgr_func && + hwmgr->hwmgr_func->update_nbdpm_pstate) + hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr, + false, + true); + } + } + image_size = width * height; image_size += image_size / 2; image_size = ALIGN(image_size, 1024); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c index 553a203..0bf56f7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c @@ -1228,8 +1228,10 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) { - if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) + if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { + smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF); + } return 0; } -- 2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
