From: Dmytro Laktyushkin <[email protected]>

[Why]
We seem to have an issue where high enough display clock
will not get set properly during S3 resume if we only
call vbios once

[How]
Expand condition of display clock programming to happen
even when cached display clock matches requested display
clock

Change-Id: I4b78dd64c97b4bd30d24958585bf3bd54a102081
Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c           | 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 04990d00a97d..51ceb9924712 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -627,7 +627,9 @@ static void dcn1_update_clocks(struct dccg *dccg,
        }
 
        /* dcn1 dppclk is tied to dispclk */
-       if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, 
dccg->clks.dispclk_khz)) {
+       /* program dispclk on = as a w/a for sleep resume clock ramping issues 
*/
+       if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, 
dccg->clks.dispclk_khz)
+                       || new_clocks->dispclk_khz == dccg->clks.dispclk_khz) {
                dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);
                dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 56f259f673f2..ba4856f3dd61 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1104,6 +1104,8 @@ static void dcn10_init_hw(struct dc *dc)
        }
 
        enable_power_gating_plane(dc->hwseq, true);
+
+       memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));
 }
 
 static void reset_hw_ctx_wrap(
-- 
2.14.1

_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to