> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Michel Dänzer > Sent: Friday, July 20, 2018 12:33 PM > To: [email protected] > Subject: [PATCH] drm/amdgpu: Fix RLC safe mode test in > gfx_v9_0_enter_rlc_safe_mode > > From: Michel Dänzer <[email protected]> > > We were testing the register offset, instead of the value stored in the > register, therefore always timing out the loop. > > This reduces suspend time of the system in the bug report below by ~600 > ms. > > Bugzilla: https://bugs.freedesktop.org/107277 > Tested-by: Paul Menzel <[email protected]> > Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 9ab39117cc4e..ef00d14f8645 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -3490,7 +3490,7 @@ static void gfx_v9_0_enter_rlc_safe_mode(struct > amdgpu_device *adev) > > /* wait for RLC_SAFE_MODE */ > for (i = 0; i < adev->usec_timeout; i++) { > - if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, > mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) > + if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, > mmRLC_SAFE_MODE), > +RLC_SAFE_MODE, CMD)) > break; > udelay(1); > } > -- > 2.18.0 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
