Reviewed-by: Evan Quan <[email protected]> -----Original Message----- From: amd-gfx [mailto:[email protected]] On Behalf Of Rex Zhu Sent: Friday, March 02, 2018 8:44 PM To: [email protected] Cc: Zhu, Rex <[email protected]> Subject: [PATCH 2/4] drm/amd/pp: Fix sclk in highest two levels in compute mode on smu7
Compute workload tends to be "bursty", Only tune the behavior of nature dpm don't work well for most of such workloads. From tests result, Fix sclk in highest two levels can get better performance. so add min sclk setting into the default cumpute workload policy on smu7. user still can change sclk range through sysfs pp_dpm_sclk for better perf/watt. Change-Id: I0ffd19a5d3c9e57f22aebd9ff1e18b980a111384 Signed-off-by: Rex Zhu <[email protected]> --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index c1e32f4..ba114482 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -5005,6 +5005,26 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) return size; } +static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, + enum PP_SMC_POWER_PROFILE requst) +{ + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + uint32_t tmp, level; + + if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { + if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { + level = 0; + tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; + while (tmp >>= 1) + level++; + if (level > 0) + smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); + } + } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { + smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); + } +} + static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -5055,6 +5075,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; data->current_profile_setting.mclk_activity = tmp.mclk_activity; } + smu7_patch_compute_profile_mode(hwmgr, mode); hwmgr->power_profile_mode = mode; } break; -- 1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
