mes_v11_0_queue_init(), mes_v12_0_queue_init(), and mes_v12_1_queue_init() clear wptr_cpu_addr in their reset/suspend paths before reinitializing the MES queue.
Those MES rings otherwise use the same writeback slot as a 64-bit wptr carrier. Clearing it through a 32-bit access resets only the low 32 bits and can leave stale high 32 bits behind, so the reset path does not necessarily produce a fully zeroed 64-bit wptr state. Use the typed 64-bit writeback helper for the MES wptr reset so the full carrier is cleared in all three queue-init paths. Signed-off-by: Runyu Xiao <[email protected]> --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 46f6dfd77..2d5baed0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1307,8 +1307,8 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev, if ((pipe == AMDGPU_MES_SCHED_PIPE) && (amdgpu_in_reset(adev) || adev->in_suspend)) { - *(ring->wptr_cpu_addr) = 0; - *(ring->rptr_cpu_addr) = 0; + amdgpu_ring_wb_write64(ring->wptr_cpu_addr, 0); + amdgpu_ring_wb_write32(ring->rptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index fb6f34b06..b397f1816 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1475,8 +1475,8 @@ static int mes_v12_0_queue_init(struct amdgpu_device *adev, if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && (amdgpu_in_reset(adev) || adev->in_suspend)) { - *(ring->wptr_cpu_addr) = 0; - *(ring->rptr_cpu_addr) = 0; + amdgpu_ring_wb_write64(ring->wptr_cpu_addr, 0); + amdgpu_ring_wb_write32(ring->rptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index b00b65090..34edb98ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -1451,8 +1451,8 @@ static int mes_v12_1_queue_init(struct amdgpu_device *adev, if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && (amdgpu_in_reset(adev) || adev->in_suspend)) { - *(ring->wptr_cpu_addr) = 0; - *(ring->rptr_cpu_addr) = 0; + amdgpu_ring_wb_write64(ring->wptr_cpu_addr, 0); + amdgpu_ring_wb_write32(ring->rptr_cpu_addr, 0); amdgpu_ring_clear_ring(ring); } -- 2.34.1
