AMD General
> -----Original Message-----
> From: Sun, Ce(Overlord) <[email protected]>
> Sent: Wednesday, July 15, 2026 3:06 PM
> To: [email protected]
> Cc: Zhang, Hawking <[email protected]>; Chai, Thomas
> <[email protected]>; Zhou1, Tao <[email protected]>; Yang, Stanley
> <[email protected]>; Sun, Ce(Overlord) <[email protected]>
> Subject: [PATCH v2] drm/amdgpu/ras: Add debug mask to disable CE logs for
> uniras
>
> Add debug mask to disable kernel logs of RAS correctable errors, including
> both ACA
> and CE error counter kernel messages.
>
> Signed-off-by: Ce Sun <[email protected]>
> ---
> drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 12 ++++++++++++
> drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 1 +
> drivers/gpu/drm/amd/ras/rascore/ras.h | 3 +++
> drivers/gpu/drm/amd/ras/rascore/ras_aca.c | 7 +++++++
> drivers/gpu/drm/amd/ras/rascore/ras_core.c | 10 ++++++++++
> 5 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> index ea95e0f93d1c..bdc9d9583bdf 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> @@ -437,6 +437,7 @@ static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block
> *ip_block)
> ras_mgr->ras_is_ready = true;
>
> amdgpu_enable_uniras(adev, true);
> + amdgpu_set_ce_log_state(adev);
>
> RAS_DEV_INFO(adev, "AMDGPU RAS Is Ready.\n");
> return 0;
> @@ -510,6 +511,17 @@ const struct amdgpu_ip_block_version ras_v1_0_ip_block
> = {
> .funcs = &ras_v1_0_ip_funcs,
> };
>
> +void amdgpu_set_ce_log_state(struct amdgpu_device *adev) {
> + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
> + bool disable_ce_log = !!adev->debug_disable_ce_logs;
> +
> + if (!ras_mgr || !ras_mgr->ras_core)
> + return;
> +
> + ras_core_disable_ce_log(ras_mgr->ras_core, disable_ce_log); }
> +
> int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable) {
> struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); diff
> --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
> b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
> index a20bb8fdce87..efbdb25241a3 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h
> @@ -63,6 +63,7 @@ extern const struct amdgpu_ip_block_version
> ras_v1_0_ip_block; struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(
> struct amdgpu_device *adev);
> int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);
> +void amdgpu_set_ce_log_state(struct amdgpu_device *adev);
> bool amdgpu_uniras_enabled(struct amdgpu_device *adev); int
> amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data);
> int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev,
> void
> *data); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h
> b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 878dfdfcb18a..0c362f9e25d6 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -346,6 +346,7 @@ struct ras_core_context {
> spinlock_t seqno_lock;
>
> bool ras_core_enabled;
> + bool ras_core_ce_log_disabled;
>
> u64 ras_fw_features;
> };
> @@ -403,4 +404,6 @@ int ras_core_convert_soc_pa_to_cur_nps_pages(struct
> ras_core_context *ras_core, int ras_core_check_address_sanity(struct
> ras_core_context *ras_core, uint64_t addr);
>
> int ras_core_set_debug_mode(struct ras_core_context *ras_core, bool enable);
> +void ras_core_disable_ce_log(struct ras_core_context *ras_core, bool
> +disable); bool ras_core_is_ce_log_disabled(struct ras_core_context
> +*ras_core);
> #endif
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> index 67a35409ff0e..7219a1008dea 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
> @@ -99,6 +99,8 @@ static void aca_report_ecc_info(struct ras_core_context
> *ras_core,
> }
>
> if (ecc_count.new_ce_count) {
> + if (ras_core_is_ce_log_disabled(ras_core))
> + return;
> RAS_DEV_INFO(ras_core->dev,
> "{%llu} socket: %d, die: %d, %u new correctable hardware errors
> detected in %s block\n",
> seq_no, skt, aid, ecc_count.new_ce_count,
> blk_name(blk));
> @@ -114,6 +116,11 @@ static void aca_bank_log(struct ras_core_context
> *ras_core, {
> int i;
>
> + if(ras_core_is_ce_log_disabled(ras_core) &&
> + bank->ecc_type == RAS_ERR_TYPE__CE &&
> + !bank_ecc->de_count)
[Tao] the de_count is always 0 for non-umc blocks.
> + return;
> +
> RAS_DEV_INFO(ras_core->dev,
> "{%llu}" RAS_HW_ERR "Accelerator Check Architecture events
> logged\n",
> bank->seq_no);
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> index 08e17a83ad5b..76cc98e0abc5 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> @@ -545,6 +545,16 @@ bool ras_core_is_enabled(struct ras_core_context
> *ras_core)
> return ras_core->ras_core_enabled;
> }
>
> +void ras_core_disable_ce_log(struct ras_core_context *ras_core, bool
> +disable) {
> + ras_core->ras_core_ce_log_disabled = disable; }
> +
> +bool ras_core_is_ce_log_disabled(struct ras_core_context *ras_core) {
> + return ras_core->ras_core_ce_log_disabled;
> +}
> +
> uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context
> *ras_core) {
> if (!ras_core)
> --
> 2.34.1
