> -----Original Message----- > From: Evan Quan [mailto:[email protected]] > Sent: Friday, October 20, 2017 4:32 AM > To: [email protected] > Cc: Zhu, Rex; Deucher, Alexander; Quan, Evan > Subject: [PATCH 1/2] drm/amd/powerplay: retrieve the real-time coreClock > values
There should be a new line here. currently, the coreClock vaule for min/max performance level on > raven is hard-coded. - use the real-time vaule retrieved by > GetGfxMinFreqLimit and GetGfxMaxFreqLimit PPSMC... Typos: vaule -> value Drop the "-" before use". E.g, s/- use/Use/ With that fixed: Acked-by: Alex Deucher <[email protected]> > > Change-Id: Ic581d8f7acc4ba7b545a611c071815a5c53f8bb5 > Signed-off-by: Evan Quan <[email protected]> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28 ++++++----------- > --------- > 1 file changed, 6 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c > index 9380108..3e0b267 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c > @@ -672,36 +672,20 @@ static int rv_get_performance_level(struct > pp_hwmgr *hwmgr, const struct pp_hw_p > PHM_PerformanceLevelDesignation > designation, uint32_t index, > PHM_PerformanceLevel *level) > { > - const struct rv_power_state *ps; > struct rv_hwmgr *data; > - uint32_t level_index; > - uint32_t i; > - uint32_t vol_dep_record_index = 0; > > if (level == NULL || hwmgr == NULL || state == NULL) > return -EINVAL; > > data = (struct rv_hwmgr *)(hwmgr->backend); > - ps = cast_const_rv_ps(state); > - > - level_index = index > ps->level - 1 ? ps->level - 1 : index; > - level->coreClock = 30000; > > - if (designation == > PHM_PerformanceLevelDesignation_PowerContainment) { > - for (i = 1; i < ps->level; i++) { > - if (ps->levels[i].engine_clock > data- > >dce_slow_sclk_threshold) { > - level->coreClock = 30000; > - break; > - } > - } > - } > - > - if (level_index == 0) { > - vol_dep_record_index = data- > >clock_vol_info.vdd_dep_on_fclk->count - 1; > - level->memory_clock = > - data->clock_vol_info.vdd_dep_on_fclk- > >entries[vol_dep_record_index].clk; > - } else { > + if (index == 0) { > level->memory_clock = data- > >clock_vol_info.vdd_dep_on_fclk->entries[0].clk; > + level->coreClock = data->gfx_min_freq_limit; > + } else { > + level->memory_clock = data- > >clock_vol_info.vdd_dep_on_fclk->entries[ > + data->clock_vol_info.vdd_dep_on_fclk->count - > 1].clk; > + level->coreClock = data->gfx_max_freq_limit; > } > > level->nonLocalMemoryFreq = 0; > -- > 2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
