From: Andrew Jiang <[email protected]>

A previous patch set the addressable timing as active + border,
when in fact, the VESA standard specifies active as equal to
addressable + border.

This patch makes the fix more correct and in line with the standard.

Signed-off-by: Andrew Jiang <[email protected]>
Reviewed-by: Andrew Jiang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 55feb16b1fd7..0aca7a3d3dd6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -850,22 +850,11 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
         */
        pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
 
-       /**
-        * KMD sends us h and v_addressable without the borders, which causes 
us sometimes to draw
-        * the blank region on-screen. Correct for this by adding the borders 
back to their
-        * respective addressable values, and by shifting recout.
-        */
-       timing->h_addressable += timing->h_border_left + timing->h_border_right;
-       timing->v_addressable += timing->v_border_top + timing->v_border_bottom;
-       pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
        pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
-       timing->v_border_top = 0;
-       timing->v_border_bottom = 0;
-       timing->h_border_left = 0;
-       timing->h_border_right = 0;
+       pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
 
-       pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable;
-       pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable;
+       pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 
timing->h_border_left + timing->h_border_right;
+       pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 
timing->v_border_top + timing->v_border_bottom;
 
        /* Taps calculations */
        if (pipe_ctx->plane_res.xfm != NULL)
-- 
2.14.1

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