On 9/24/2025 6:38 AM, Timur Kristóf wrote:
Reject modes with a pixel clock higher than the maximum display
clock. These were never supported, but we haven't noticed the
issue until the YCbCr 422 fallback was recently added.
For example, the DP 1.2 standard technically supports
4K 120Hz YCbCr 422 6 bpc, but in practice the pixel clock is
too high on these old GPUs.
Additionally, there are two small code cleanup patches to avoid
excessive code duplication.
Timur Kristóf (3):
drm/amd/display: Reject modes with too high pixel clock on DCE6-10
drm/amd/display: Share dce100_validate_bandwidth with DCE6-8
drm/amd/display: Share dce100_validate_global with DCE6-8
.../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 ++
.../dc/resource/dce100/dce100_resource.c | 25 +++++--
.../dc/resource/dce100/dce100_resource.h | 9 +++
.../dc/resource/dce60/dce60_resource.c | 69 +------------------
.../dc/resource/dce80/dce80_resource.c | 60 +---------------
6 files changed, 44 insertions(+), 127 deletions(-)
I've applied this internally and it will run through CI and come to
amd-staging-drm-next soon, thanks!
