From: Dillon Varone <dillon.var...@amd.com>

[WHY&HOW]
SMU interfaces are not backwards and forwards compatible, so they should
be isolated per version.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
Signed-off-by: Ivan Lipski <ivan.lip...@amd.com>
---
 .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c        |  26 ++--
 .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c   | 118 ++++++++++++++++++
 .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h   |  10 +-
 3 files changed, 140 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 47461f249e83..306016c1f109 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -162,7 +162,7 @@ static void dcn401_init_single_clock(struct 
clk_mgr_internal *clk_mgr, PPCLK_e c
        unsigned int i;
        char *entry_i = (char *)entry_0;
 
-       uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
+       uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
 
        if (ret & (1 << 31))
                /* fine-grained, only min and max */
@@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct 
clk_mgr_internal *clk_mgr, PPCLK_e c
 
        /* if the initial message failed, num_levels will be 0 */
        for (i = 0; i < *num_levels && i < 
ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
-               *((unsigned int *)entry_i) = 
(dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
+               *((unsigned int *)entry_i) = 
(dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
                entry_i += 
sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
        }
 }
@@ -231,20 +231,20 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
        clk_mgr->smu_present = false;
        clk_mgr->dpm_present = false;
 
-       if (!clk_mgr_base->force_smu_not_present && 
dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
+       if (!clk_mgr_base->force_smu_not_present && 
dcn401_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
                clk_mgr->smu_present = true;
 
        if (!clk_mgr->smu_present)
                return;
 
-       dcn30_smu_check_driver_if_version(clk_mgr);
-       dcn30_smu_check_msg_header_version(clk_mgr);
+       dcn401_smu_check_driver_if_version(clk_mgr);
+       dcn401_smu_check_msg_header_version(clk_mgr);
 
        /* DCFCLK */
        dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
                        
&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
                        &num_entries_per_clk->num_dcfclk_levels);
-       clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
+       clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
        if (num_entries_per_clk->num_dcfclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
                        
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels
 - 1].dcfclk_mhz)
                clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
@@ -253,7 +253,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
        dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
                                        
&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
                                        
&num_entries_per_clk->num_socclk_levels);
-       clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
+       clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
        if (num_entries_per_clk->num_socclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
                        
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels
 - 1].socclk_mhz)
                clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
@@ -263,7 +263,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
                dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
                                
&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
                                &num_entries_per_clk->num_dtbclk_levels);
-               clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
+               clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
                if (num_entries_per_clk->num_dtbclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
                                
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels
 - 1].dtbclk_mhz)
                        clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
@@ -273,7 +273,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
        dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
                        
&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
                        &num_entries_per_clk->num_dispclk_levels);
-       clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
+       clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
        if (num_entries_per_clk->num_dispclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
                        
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels
 - 1].dispclk_mhz)
                clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
@@ -1318,8 +1318,8 @@ static void dcn401_notify_wm_ranges(struct clk_mgr 
*clk_mgr_base)
                        table->Watermarks.WatermarkRow[i].WmSetting = i;
                        table->Watermarks.WatermarkRow[i].Flags = 
clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
                }
-       dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 
32);
-       dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 
0xFFFFFFFF);
+       dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 
32);
+       dcn401_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 
0xFFFFFFFF);
        dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 }
 
@@ -1390,7 +1390,7 @@ static void dcn401_get_memclk_states_from_smu(struct 
clk_mgr *clk_mgr_base)
                                
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels
 - 1].memclk_mhz;
        }
 
-       clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
+       clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
        if (num_entries_per_clk->num_memclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
                        
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels
 - 1].memclk_mhz)
                clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
@@ -1399,7 +1399,7 @@ static void dcn401_get_memclk_states_from_smu(struct 
clk_mgr *clk_mgr_base)
        dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
                        &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
                        &num_entries_per_clk->num_fclk_levels);
-       clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
+       clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 
dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
        if (num_entries_per_clk->num_fclk_levels && 
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
                        
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels 
- 1].fclk_mhz)
                clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;
diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
index 21c35528f61f..347a0d66d653 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
@@ -139,6 +139,59 @@ static bool dcn401_smu_send_msg_with_param_delay(struct 
clk_mgr_internal *clk_mg
        return false;
 }
 
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int 
*version)
+{
+       smu_print("SMU Get SMU version\n");
+
+       if (dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_GetSmuVersion, 0, version)) {
+
+               smu_print("SMU version: %d\n", *version);
+
+               return true;
+       }
+
+       return false;
+}
+
+/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
+bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
+{
+       uint32_t response = 0;
+
+       smu_print("SMU Check driver if version\n");
+
+       if (dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
+
+               smu_print("SMU driver if version: %d\n", response);
+
+               if (response == SMU14_DRIVER_IF_VERSION)
+                       return true;
+       }
+
+       return false;
+}
+
+/* Message output should match DALSMC_VERSION in dalsmc.h */
+bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
+{
+       uint32_t response = 0;
+
+       smu_print("SMU Check msg header version\n");
+
+       if (dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
+
+               smu_print("SMU msg header version: %d\n", response);
+
+               if (response == DALSMC_VERSION)
+                       return true;
+       }
+
+       return false;
+}
+
 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, 
bool support)
 {
        smu_print("FCLK P-state support value is : %d\n", support);
@@ -163,6 +216,22 @@ void dcn401_smu_send_cab_for_uclk_message(struct 
clk_mgr_internal *clk_mgr, unsi
        smu_print("Numways for SubVP : %d\n", num_ways);
 }
 
+void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_high)
+{
+       smu_print("SMU Set DRAM addr high: %d\n", addr_high);
+
+       dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
+}
+
+void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_low)
+{
+       smu_print("SMU Set DRAM addr low: %d\n", addr_low);
+
+       dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
+}
+
 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 {
        smu_print("SMU Transfer WM table DRAM 2 SMU\n");
@@ -348,3 +417,52 @@ unsigned int dcn401_smu_get_num_of_umc_channels(struct 
clk_mgr_internal *clk_mgr
 
        return response;
 }
+
+/*
+ * Frequency in MHz returned in lower 16 bits for valid DPM level
+ *
+ * Call with dpm_level = 0xFF to query features, return value will be:
+ *     Bits 7:0 - number of DPM levels
+ *     Bit   28 - 1 = auto DPM on
+ *     Bit   29 - 1 = sweep DPM on
+ *     Bit   30 - 1 = forced DPM on
+ *     Bit   31 - 0 = discrete, 1 = fine-grained
+ *
+ * With fine-grained DPM, only min and max frequencies will be reported
+ *
+ * Returns 0 on failure
+ */
+unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal 
*clk_mgr, uint32_t clk, uint8_t dpm_level)
+{
+       uint32_t response = 0;
+
+       /* bits 23:16 for clock type, lower 8 bits for DPM level */
+       uint32_t param = (clk << 16) | dpm_level;
+
+       smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, 
dpm_level);
+
+       dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_GetDpmFreqByIndex, param, &response);
+
+       smu_print("SMU dpm freq: %d MHz\n", response);
+
+       return response;
+}
+
+/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
+unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal 
*clk_mgr, uint32_t clk)
+{
+       uint32_t response = 0;
+
+       /* bits 23:16 for clock type */
+       uint32_t param = clk << 16;
+
+       smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
+
+       dcn401_smu_send_msg_with_param(clk_mgr,
+                       DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
+
+       smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
+
+       return response;
+}
diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
index e02eb1294b37..4f5ac603e822 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
@@ -7,11 +7,17 @@
 
 #include "os_types.h"
 #include "core_types.h"
-#include "dcn32/dcn32_clk_mgr_smu_msg.h"
 
+struct clk_mgr_internal;
+
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int 
*version);
+bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
+bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, 
bool support);
 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, 
bool support);
 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, 
unsigned int num_ways);
+void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_high);
+void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_low);
 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
 unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, 
uint32_t clk, uint16_t freq_mhz);
@@ -29,5 +35,7 @@ bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct 
clk_mgr_internal *clk_mgr,
 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, 
uint32_t freq_mhz);
 void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t 
num_displays);
 unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal 
*clk_mgr);
+unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal 
*clk_mgr, uint32_t clk);
+unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal 
*clk_mgr, uint32_t clk, uint8_t dpm_level);
 
 #endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */
-- 
2.43.0

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