> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Christian König > Sent: Thursday, September 21, 2017 4:32 AM > To: Christian König; [email protected] > Subject: Re: [PATCH] drm/amdgpu: simplify pinning into visible VRAM > > Ping?
Reviewed-by: Alex Deucher <[email protected]> > > Am 13.09.2017 um 10:32 schrieb Christian König: > > From: Christian König <[email protected]> > > > > Just set the CPU access required flag when we pin it. > > > > Signed-off-by: Christian König <[email protected]> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 23 ++++++++----------- > ---- > > 1 file changed, 8 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > > index 726a662..6982bae 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > > @@ -635,7 +635,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo > *bo, u32 domain, > > { > > struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); > > int r, i; > > - unsigned fpfn, lpfn; > > > > if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) > > return -EPERM; > > @@ -667,22 +666,16 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo > *bo, u32 domain, > > } > > > > bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; > > + /* force to pin into visible video ram */ > > + if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) > > + bo->flags |= > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; > > amdgpu_ttm_placement_from_domain(bo, domain); > > for (i = 0; i < bo->placement.num_placement; i++) { > > - /* force to pin into visible video ram */ > > - if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && > > - !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) > && > > - (!max_offset || max_offset > > > - adev->mc.visible_vram_size)) { > > - if (WARN_ON_ONCE(min_offset > > > - adev->mc.visible_vram_size)) > > - return -EINVAL; > > - fpfn = min_offset >> PAGE_SHIFT; > > - lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; > > - } else { > > - fpfn = min_offset >> PAGE_SHIFT; > > - lpfn = max_offset >> PAGE_SHIFT; > > - } > > + unsigned fpfn, lpfn; > > + > > + fpfn = min_offset >> PAGE_SHIFT; > > + lpfn = max_offset >> PAGE_SHIFT; > > + > > if (fpfn > bo->placements[i].fpfn) > > bo->placements[i].fpfn = fpfn; > > if (!bo->placements[i].lpfn || > > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
