ping on this series.
On Fri, Jul 11, 2025 at 6:28 PM Alex Deucher <[email protected]> wrote: > > Set the MQD as appropriate for the queue priv state. > > Acked-by: Christian König <[email protected]> > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > index e4fc42470cf3e..c4dc6bfb0f6f1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > @@ -3016,6 +3016,8 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device > *adev, void *m, > #endif > if (prop->tmz_queue) > tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); > + if (!prop->priv_queue) > + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); > mqd->cp_gfx_hqd_cntl = tmp; > > /* set up cp_doorbell_control */ > @@ -3165,8 +3167,10 @@ static int gfx_v12_0_compute_mqd_init(struct > amdgpu_device *adev, void *m, > (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); > tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); > tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); > - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); > - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); > + if (prop->priv_queue) { > + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); > + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); > + } > if (prop->tmz_queue) > tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); > mqd->cp_hqd_pq_control = tmp; > -- > 2.50.0 >
