[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Zhigang Luo <[email protected]>
> -----Original Message----- > From: Yi, Tony <[email protected]> > Sent: Friday, June 20, 2025 11:55 AM > To: Yi, Tony <[email protected]>; Skvortsov, Victor <[email protected]>; > [email protected]; Zhang, Hawking <[email protected]>; Luo, > Zhigang <[email protected]>; Gande, Shravan kumar > <[email protected]>; Chan, Hing Pong <[email protected]> > Cc: Yi, Tony <[email protected]> > Subject: [PATCH] drm/amdgpu: Check SQ_CONFIG register support on SRIOV > > On SRIOV environments, check if RLCG supports SQ_CONFIG register > programming. > > Signed-off-by: Tony Yi <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8 +++++++- > drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +++- > 3 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > index 9320461bb486..3da3ebb1d9a1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > @@ -152,8 +152,10 @@ enum AMDGIM_REG_ACCESS_FLAG { > AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), > /* Use RLC to program GC regs */ > AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), > - /* Use PSP to program L1_TLB_CNTL*/ > + /* Use PSP to program L1_TLB_CNTL */ > AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3), > + /* Use RLCG to program SQ_CONFIG1 */ > + AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4), > }; > > struct amdgim_pf2vf_info_v1 { > @@ -346,6 +348,10 @@ struct amdgpu_video_codec_info; #define > amdgpu_sriov_rlcg_error_report_enabled(adev) \ > (amdgpu_sriov_reg_indirect_mmhub(adev) || > amdgpu_sriov_reg_indirect_gc(adev)) > > +#define amdgpu_sriov_reg_access_sq_config(adev) \ > +(amdgpu_sriov_vf((adev)) && \ > + ((adev)->virt.reg_access & > (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG))) > + > #define amdgpu_passthrough(adev) \ > ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h > b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h > index 92ca13097aaa..33edad1f9dcd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h > @@ -113,7 +113,8 @@ union amd_sriov_reg_access_flags { > uint32_t vf_reg_access_mmhub : 1; > uint32_t vf_reg_access_gc : 1; > uint32_t vf_reg_access_l1_tlb_cntl : 1; > - uint32_t reserved : 28; > + uint32_t vf_reg_access_sq_config : 1; > + uint32_t reserved : 27; > } flags; > uint32_t all; > }; > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > index c233edf60569..4a5fc5b8ac6a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > @@ -1349,7 +1349,9 @@ static void gfx_v9_4_3_constants_init(struct > amdgpu_device *adev) > switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { > /* ToDo: GC 9.4.4 */ > case IP_VERSION(9, 4, 3): > - if (adev->gfx.mec_fw_version >= 184) > + if (adev->gfx.mec_fw_version >= 184 && > + (amdgpu_sriov_reg_access_sq_config(adev) || > + !amdgpu_sriov_vf(adev))) > adev->gmc.xnack_flags |= > AMDGPU_GMC_XNACK_FLAG_CHAIN; > break; > case IP_VERSION(9, 5, 0): > -- > 2.34.1
