From: Leo Chen <[email protected]> [Why & How] To facilitate debugging, the following behaviors are defined for existing debug option disable_ips_in_vpb
0 - Enable IPS in LVP - let driver decide (legacy) 1 - Disable IPS in LVP 2 - Enable IPS1 and RCG in LVP 3 - Enable IPS1 Z8, IPS1 and RCG in LVP Reviewed-by: Duncan Ma <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 7 +++++++ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index b4525b1fc11b..f5ef1a07078e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1314,6 +1314,13 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) } else if (dc->config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) { new_signals.bits.allow_ips0_rcg = 1; } + // IPS dynamic allow bits (IPSv2 change, vpb use case) + if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) { + new_signals.bits.allow_dynamic_ips1 = 1; + } else if (dc->config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) { + new_signals.bits.allow_dynamic_ips1 = 1; + new_signals.bits.allow_dynamic_ips1_z8 = 1; + } ips_driver->signals = new_signals; dc_dmub_srv->driver_signals = ips_driver->signals; } diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 938a07cdcfec..fed2d3999305 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -790,6 +790,13 @@ enum dmub_ips_rcg_disable_type { DMUB_IPS_RCG_DISABLE = 3 }; +enum dmub_ips_in_vpb_disable_type { + DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour + DMUB_IPS_VPB_DISABLE_ALL = 1, + DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, + DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG +}; + #define DMUB_IPS1_ALLOW_MASK 0x00000001 #define DMUB_IPS2_ALLOW_MASK 0x00000002 #define DMUB_IPS1_COMMIT_MASK 0x00000004 -- 2.43.0
