Hi Alex,
On 6/17/2025 8:38 AM, Alex Deucher wrote:
Use the new helpers to handle engine resets for VCN.
Untested.
Signed-off-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9fb0d53805892..ec4d2ab75fc4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -110,6 +110,7 @@ static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst
*vinst,
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
struct dpg_pause_state *new_state);
+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst);
static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
@@ -289,6 +290,7 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block
*ip_block)
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.inst[i].pause_dpg_mode =
vcn_v3_0_pause_dpg_mode;
+ adev->vcn.inst[i].reset = vcn_v3_0_reset;
}
if (amdgpu_sriov_vf(adev)) {
@@ -1869,6 +1871,7 @@ static const struct amdgpu_ring_funcs
vcn_v3_0_dec_sw_ring_vm_funcs = {
.emit_wreg = vcn_dec_sw_ring_emit_wreg,
.emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
You probably wanted to add reset callback to vcn_v3_0_enc_ring_vm_funcs
instead ofvcn_v3_0_dec_sw_ring_vm_funcs.
With that, the vcn and jpeg changes in this series are :-
Reviewed-by: Sathishkumar S <[email protected]>
Tested-by: Sathishkumar S <[email protected]>
Test exceptions: VCN/JPEG 4_0_3 and VCN/JPEG 5_0_1.
Regards,
Sathish
};
static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
@@ -2033,6 +2036,7 @@ static const struct amdgpu_ring_funcs
vcn_v3_0_dec_ring_vm_funcs = {
.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ .reset = amdgpu_vcn_ring_reset,
};
/**
@@ -2164,6 +2168,26 @@ static void vcn_v3_0_set_enc_ring_funcs(struct
amdgpu_device *adev)
}
}
+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst)
+{
+ int i, r;
+
+ vcn_v3_0_stop(vinst);
+ vcn_v3_0_start(vinst);
+ r = amdgpu_ring_test_ring(&vinst->ring_dec);
+ if (r)
+ return r;
+ for (i = 0; i < vinst->num_enc_rings; i++) {
+ r = amdgpu_ring_test_ring(&vinst->ring_enc[i]);
+ if (r)
+ return r;
+ }
+ amdgpu_fence_driver_force_completion(&vinst->ring_dec);
+ for (i = 0; i < vinst->num_enc_rings; i++)
+ amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]);
+ return 0;
+}
+
static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
