[Public] > -----Original Message----- > From: amd-gfx <[email protected]> On Behalf Of Mario > Limonciello > Sent: Sunday, June 8, 2025 11:12 PM > To: [email protected] > Cc: Limonciello, Mario <[email protected]>; Pierre-Loup A . Griffais > <[email protected]>; Vicki Pfau <[email protected]> > Subject: [PATCH v2 1/2] drm/amd: Allow printing VanGogh OD SCLK levels without > setting dpm to manual > > From: Mario Limonciello <[email protected]> > > Several other ASICs allow printing OD SCLK levels without setting DPM control > to > manual. When OD is disabled it will show the range the hardware supports. > When > OD is enabled it will show what values have been programmed. Adjust VanGogh to > work the same. > > Cc: Pierre-Loup A. Griffais <[email protected]> > Reported-by: Vicki Pfau <[email protected]> > Signed-off-by: Mario Limonciello <[email protected]>
Series is: Reviewed-by: Alex Deucher <[email protected]> > --- > v1: https://lore.kernel.org/amd-gfx/20250323145316.859797-1- > [email protected]/ > v1 (resend): https://lore.kernel.org/amd-gfx/20250421210639.1138228-1- > [email protected]/ > v2: rebase > --- > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 37 ++++++++----------- > 1 file changed, 15 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > index a55ea76d73996..2c9869feba610 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c > @@ -666,7 +666,6 @@ static int vangogh_print_clk_levels(struct smu_context > *smu, { > DpmClocks_t *clk_table = smu->smu_table.clocks_table; > SmuMetrics_t metrics; > - struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); > int i, idx, size = 0, ret = 0; > uint32_t cur_value = 0, value = 0, count = 0; > bool cur_value_match_level = false; > @@ -682,31 +681,25 @@ static int vangogh_print_clk_levels(struct smu_context > *smu, > > switch (clk_type) { > case SMU_OD_SCLK: > - if (smu_dpm_ctx->dpm_level == > AMD_DPM_FORCED_LEVEL_MANUAL) { > - size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); > - size += sysfs_emit_at(buf, size, "0: %10uMhz\n", > - (smu->gfx_actual_hard_min_freq > 0) ? smu- > >gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); > - size += sysfs_emit_at(buf, size, "1: %10uMhz\n", > - (smu->gfx_actual_soft_max_freq > 0) ? smu- > >gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); > - } > + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); > + size += sysfs_emit_at(buf, size, "0: %10uMhz\n", > + (smu->gfx_actual_hard_min_freq > 0) ? smu- > >gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); > + size += sysfs_emit_at(buf, size, "1: %10uMhz\n", > + (smu->gfx_actual_soft_max_freq > 0) ? smu- > >gfx_actual_soft_max_freq : > +smu->gfx_default_soft_max_freq); > break; > case SMU_OD_CCLK: > - if (smu_dpm_ctx->dpm_level == > AMD_DPM_FORCED_LEVEL_MANUAL) { > - size += sysfs_emit_at(buf, size, "CCLK_RANGE in > Core%d:\n", smu->cpu_core_id_select); > - size += sysfs_emit_at(buf, size, "0: %10uMhz\n", > - (smu->cpu_actual_soft_min_freq > 0) ? smu- > >cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); > - size += sysfs_emit_at(buf, size, "1: %10uMhz\n", > - (smu->cpu_actual_soft_max_freq > 0) ? smu- > >cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq); > - } > + size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", > smu->cpu_core_id_select); > + size += sysfs_emit_at(buf, size, "0: %10uMhz\n", > + (smu->cpu_actual_soft_min_freq > 0) ? smu- > >cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq); > + size += sysfs_emit_at(buf, size, "1: %10uMhz\n", > + (smu->cpu_actual_soft_max_freq > 0) ? smu- > >cpu_actual_soft_max_freq : > +smu->cpu_default_soft_max_freq); > break; > case SMU_OD_RANGE: > - if (smu_dpm_ctx->dpm_level == > AMD_DPM_FORCED_LEVEL_MANUAL) { > - size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); > - size += sysfs_emit_at(buf, size, "SCLK: %7uMhz > %10uMhz\n", > - smu->gfx_default_hard_min_freq, smu- > >gfx_default_soft_max_freq); > - size += sysfs_emit_at(buf, size, "CCLK: %7uMhz > %10uMhz\n", > - smu->cpu_default_soft_min_freq, smu- > >cpu_default_soft_max_freq); > - } > + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); > + size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", > + smu->gfx_default_hard_min_freq, smu- > >gfx_default_soft_max_freq); > + size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", > + smu->cpu_default_soft_min_freq, smu- > >cpu_default_soft_max_freq); > break; > case SMU_SOCCLK: > /* the level 3 ~ 6 of socclk use the same frequency for vangogh > */ > -- > 2.43.0
