We need to take the MES lock.

Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index a4f2be39c237f..bf375687613a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -303,7 +303,9 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
        if (ring == &adev->mes.ring[AMDGPU_MES_SCHED_PIPE])
                queue_input.use_kiq = true;
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                DRM_ERROR("failed to map legacy queue\n");
 
@@ -330,7 +332,9 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device 
*adev,
        if (ring == &adev->mes.ring[AMDGPU_MES_SCHED_PIPE])
                queue_input.use_kiq = true;
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                DRM_ERROR("failed to unmap legacy queue\n");
 
@@ -359,7 +363,9 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device 
*adev,
        if (ring->funcs->type == AMDGPU_RING_TYPE_GFX)
                queue_input.legacy_gfx = true;
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                DRM_ERROR("failed to reset legacy queue\n");
 
@@ -389,7 +395,9 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, 
uint32_t reg)
                goto error;
        }
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                dev_err(adev->dev, "failed to read reg (0x%x)\n", reg);
        else
@@ -417,7 +425,9 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
                goto error;
        }
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                dev_err(adev->dev, "failed to write reg (0x%x)\n", reg);
 
@@ -444,7 +454,9 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device 
*adev,
                goto error;
        }
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                dev_err(adev->dev, "failed to reg_write_reg_wait\n");
 
@@ -469,7 +481,9 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, 
uint32_t reg,
                goto error;
        }
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                dev_err(adev->dev, "failed to reg_write_reg_wait\n");
 
@@ -700,7 +714,9 @@ static int amdgpu_mes_set_enforce_isolation(struct 
amdgpu_device *adev,
                goto error;
        }
 
+       amdgpu_mes_lock(&adev->mes);
        r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       amdgpu_mes_unlock(&adev->mes);
        if (r)
                dev_err(adev->dev, "failed to change_config.\n");
 
-- 
2.49.0

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