[PATCH v2 7/9] drm/amdgpu: read back register after written

[David (Ming Qiang) Wu]

The addition of register read-back in VCN v4.0.5 is intended to prevent
potential race conditions.

Signed-off-by: David (Ming Qiang) Wu <david....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index a09f9a2dd471..46dced751249 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1034,9 +1034,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct 
amdgpu_vcn_inst *vinst,
                        ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
                        VCN_RB1_DB_CTRL__EN_MASK);
 
-       /* Keeping one read-back to ensure all register writes are done, 
otherwise
-        * it may introduce race conditions */
-       RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);
 
        return 0;
 }
@@ -1220,9 +1221,10 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst 
*vinst)
        WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
        fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | 
FW_QUEUE_DPG_HOLD_OFF);
 
-       /* Keeping one read-back to ensure all register writes are done, 
otherwise
-        * it may introduce race conditions */
-       RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, i, regUVD_STATUS);
 
        return 0;
 }
@@ -1254,6 +1256,11 @@ static void vcn_v4_0_5_stop_dpg_mode(struct 
amdgpu_vcn_inst *vinst)
        /* disable dynamic power gating mode */
        WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
                ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
+
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);
 }
 
 /**
@@ -1337,6 +1344,11 @@ static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst)
        /* enable VCN power gating */
        vcn_v4_0_5_enable_static_power_gating(vinst);
 
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, i, regUVD_STATUS);
+
 done:
        if (adev->pm.dpm_enabled)
                amdgpu_dpm_enable_vcn(adev, false, i);
-- 
2.49.0