On 4/21/2025 6:39 PM, Alex Deucher wrote:
> On Mon, Apr 21, 2025 at 5:48 AM Lijo Lazar <[email protected]> wrote:
>>
>> APUs in passthrough mode use HDP flush. 0x7F000 offset used for
>> remapping HDP flush is mapped to VPE space which could get power gated.
>> Use another unused offset in BIF space.
>>
>> Signed-off-by: Lijo Lazar <[email protected]>
>
> Assuming we have a full 4k at that offset:
>
Yes, 4K size is available.
Thanks,
Lijo
> Acked-by: Alex Deucher <[email protected]>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
>> index 2ece3ae75ec1..bed5ef4d8788 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
>> @@ -360,7 +360,7 @@ static void nbio_v7_11_get_clockgating_state(struct
>> amdgpu_device *adev,
>> *flags |= AMD_CG_SUPPORT_BIF_LS;
>> }
>>
>> -#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
>> +#define MMIO_REG_HOLE_OFFSET 0x44000
>>
>> static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev)
>> {
>> --
>> 2.25.1
>>
